Abstract
Pass transistor logic is a promising alternative to conventional CMOS logic for low-power high-performance applications due to the decreased node capacitance and reduced transistor count it offers. However, the lack of supporting design automation tools has hindered the widespread application of pass transistors. In this paper, a simple and robust modeling technique for the timing analysis of the basic pass transistor structure is presented. The proposed methodology is based on the actual phenomena that govern the operation of the pass transistor and enables fast timing simulation of circuits that employ pass transistors as controlled switches without significant loss of accuracy, compared to SPICE simulation.
This work was supported by AMDREL project, IST-2001-34379, funded by the “European Union”
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Nikolaidis, S., Pournara, H., Chatzigeorgiou, A. (2002). Output Waveform Evaluation of Basic Pass Transistor Structure. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_23
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DOI: https://doi.org/10.1007/3-540-45716-X_23
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