Abstract
Wire load has become an important variable for power and timing optimization. As standard cell geometries are shrinking and average wirelength increases due to increasing design complexities wire capacitance has become dominant over gate capacitance. However the wire load of a net not only depends on wirelength but also on which metal layer a net is routed. In this paper we investigate the characteristics of metal layers and propose a power driven routing scheme, which exploits the different metal layer properties in deep submicron semicustom design flows. Layer assignment for final routing will be done according to the switching activity of a net and the layer characteristics. In section 3 we describe the investigation of the characteristics of routing layers. A parameter for the validation of metal layers for use in routing for low-power is derived. In sections 4 and 5 an objective function for power driven routing and the layer assignment methodology is described.
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References
A.-C. Deng, “Power Analysis For CMOS/BiCMOS Circuits”, International Workshop on Low Power Design, p. 3–8, 1994
M. A. Ortega, J. Figueras, “Short Circuit Power Modeling in Submicron CMOS”, Proceedings of PATMOS’96, p. 147–166, 1996
M. Pedram, B. T. Preas, “Interconnection Analysis for Standard Cell Layouts”, in IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 18, No. 10, 1999.
Semiconductor Industry Association, National Technology Roadmap for Semiconductors, p. 101, 1997.
P. Saxena, C. L. Liu, “Optimization of the Maximum Delay of Global Interconnects During Layer Assignment”, IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 20, No. 4, p. 503–515, 2001.
A. B. Kahng, D. Stroobandt, “Wiring Layer Assignment with Consistent Stage Delays”, Proceedings of the Int. Workshop on System-Level Interconnect Prediction, p. 115–122, Kluwer Academic Publishers, 2000.
A. P. Chandrakasan, R. W. Brodersen, Low Power Digital CMOS Design, p. 256, Kluwer Academic Publishers, 1995.
A. Bellaouar, M. I. Elmasry, Low-Power Digital VLSI Design, p. 490, Kluwer Academic Publishers, 1995.
H. Vaishnav, M. Pedram, “PCUBE: A Performance Driven Placement Algorithm for Low Power Designs”, Proceedings of the EURO-DAC, p. 72–77, 1993.
M. Laurent, M. Briet, “Chapter 3: Low Power Design Flow And Libraries”, Low Power Design in Deep Submicron Electronics, edited by W. Nebel and J. Mermet, p. 65, Kluwer Academic Publishers, 1997.
T. Sakurai, K. Tamaru, “Simple Formulas for Two-and Three-Dimensional Capacitances”, IEEE Transactions on Electron Devices, Vol. ED-30, No. 2, p. 183–185, 1983.
Integrated Circuit Engineering Corporation, Status 1999— A Report On The Integrated Circuit Industry, p. 8–18, 1999.
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© 2002 Springer-Verlag Berlin Heidelberg
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Windschiegl, A., Zuber, P., Stechele, W. (2002). Exploiting Metal Layer Characteristics for Low-Power Routing. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_6
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DOI: https://doi.org/10.1007/3-540-45716-X_6
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