Abstract
Formal Description Techniques (FDT), such as LOTOS or SDL are at the base of a technology for the specification and the validation of telecommunication systems. Due to the availability of commercial tools, these formalisms are now being widely used in the industrial community. Alternatively, a number of quite effcient verification tools have been developed by the research community. But, most of these tools are based on simple ad hoc formalisms and the gap between them and real fdt restricts their use at industrial scale.
This context motivated the development of an intermediate representation called if which is presented in the paper. if has a simple syntactic structure, but allows to express in a convenient way most useful concepts needed for the specification of timed asynchronous systems. The benefits of using if are multiples. First, it is general enough to handle significant subsets of most fdts, and in particular a translation from sdl to if is already implemented. Being built upon a mathematically sound model (extended timed automata) it allows to properly evaluate different semantics for fdts, in particular with respect to time considerations. Finally, if can serve as a basis for interconnecting various tools into a unified validation framework. Several levels of if program representations are already available via well defined apis and allow to connect tools ranging from static analyzers to model-checkers.
Verimag is Research Laboratory of CNRS, Université Joseph Fourier and Institut National Polytechnique of Grenoble
Work partially supported by Région Rhône-Alpes, France
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Bozga, M., Fernandez, JC., Ghirvu, L., Graf, S., Krimm, JP., Mounier, L. (1999). If: An Intermediate Representation and Validation Environment for Timed Asynchronous Systems. In: Wing, J.M., Woodcock, J., Davies, J. (eds) FM’99 — Formal Methods. FM 1999. Lecture Notes in Computer Science, vol 1708. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48119-2_19
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