Abstract
We present a simple and powerful method for formal verification of hardware that exploits hardware symmetries. We illustrate the method at an industrial example: a fragment of the IBM S/390 Clock Chip.
Partially supported by grant Ku 966/3-1 of the Deutsche Forschungsgemeinschaft within the Schwerpunkt Deduktion at the University of Tübingen.
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Geser, A., Küchlin, W. (1999). Structured Formal Verification of a Fragment of the IBM S/390 Clock Chip. In: Hutter, D., Stephan, W., Traverso, P., Ullmann, M. (eds) Applied Formal Methods — FM-Trends 98. FM-Trends 1998. Lecture Notes in Computer Science, vol 1641. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48257-1_5
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DOI: https://doi.org/10.1007/3-540-48257-1_5
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