Abstract
This paper considers a formally derived architecture of a systolic processor which directly executes the algorithm of two-dimensional N1×N2-point DFT. The systolic processor contains a N1×N2-array of orthogonally-connected processor elements of the same type and carries out O(N1N2(N1+N2)) complex operations of the algorithm in the time O(N1+N2). The described design solution meets basic implementation requirements of VLSI-based hardware.
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© 1990 Springer-Verlag Berlin Heidelberg
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Sedukhin, S.G. (1990). Systolic array architecture for two-dimensional discrete Fourier transform. In: Burkhart, H. (eds) CONPAR 90 — VAPP IV. VAPP CONPAR 1990 1990. Lecture Notes in Computer Science, vol 457. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-53065-7_144
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DOI: https://doi.org/10.1007/3-540-53065-7_144
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