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Architectures for self-learning neural network modules

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New Trends in Neural Computation (IWANN 1993)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 686))

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Abstract

The pRAM (probabilistic RAM) models the non-linear and stochastic features found in biological neurons. The pRAM is realisable in hardware and the fourth generation VLSI pRAM chip is described here. This chip contains 256 pRAM neurons and learning algorithms are built into the hardware. Several such chips can be connected together to form larger nets.

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References

  1. “Hardware realisable models of neural processing”, T G Clarkson, D Gorse and J G Taylor, Proc. 1st IEE Int. Conf. on Artificial Neural Networks, London, 242–246, 1989.

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  2. “From Wetware to Hardware: Reverse Engineering using Probabilistic RAMs”, Clarkson T G, Gorse D and Taylor J G, Special Issue: “Advances in Digital Neural Networks”, Journal of Intelligent Systems, 4, 11–30, Freund, London, 1992.

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  3. “Generalisation in Probabilistic RAM Nets”, Clarkson T G, Gorse D and Taylor J G, IEEE Transactions on Neural Networks (in print).

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  4. “Learning Probabilistic RAM Nets Using VLSI Structures”, Clarkson T G, Gorse D, Taylor J G, Ng C K, IEEE Transactions on Computers, Vol. 41, 12, 1992.

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José Mira Joan Cabestany Alberto Prieto

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© 1993 Springer-Verlag Berlin Heidelberg

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Clarkson, T.G., Ng, C.K. (1993). Architectures for self-learning neural network modules. In: Mira, J., Cabestany, J., Prieto, A. (eds) New Trends in Neural Computation. IWANN 1993. Lecture Notes in Computer Science, vol 686. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56798-4_190

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  • DOI: https://doi.org/10.1007/3-540-56798-4_190

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-56798-1

  • Online ISBN: 978-3-540-47741-9

  • eBook Packages: Springer Book Archive

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