Abstract
The implementation of larger digital neural networks has not been possible due to the real-estate requirements of single neurons. We present an expandable digital architecture which allows fast and spaceefficient computation of the sum of weighted inputs, providing an efficient implementation base for large neural networks. The actual digital circuitry is simple and highly regular, thus allowing very efficient space usage of fine grained FPGAs. We take advantage of the re-programmability of the devices to automatically generate new custom hardware for each topology of the neural network.
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© 1994 Springer-Verlag Berlin Heidelberg
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Salapura, V., Gschwind, M., Maischberger, O. (1994). A fast FPGA implementation of a general purpose neuron. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_88
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DOI: https://doi.org/10.1007/3-540-58419-6_88
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