Abstract
This paper discusses benchmarks for optimization to table-lookup FPGAs. We discuss a scientific method for systematically generating a set of benchmarks for measuring the effectiveness of a synthesis tool/algorithm for a particular FPGA architecture. The benchmarks have the useful properties of being generated easily, having an a priori, known best result, covering all the possible configurations of a lookup table, and yielding a simple metric. This metric can be used to compare different synthesis tools/algorithms for their efficiency in mapping to a given FPGA architecture. This is in contrast to the ad hoc sets of benchmarks, for which it is difficult to compare results of different optimization tools/algorithms.
References
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Steve Trimberger: A Small, Complete Mapping Library for Lookup-Table-Based FPGAs. In the 2nd International Workshop on Field-Programmable Logic and Applications. IFIP Working Groups 10.2 and 10.5, August 1992
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© 1994 Springer-Verlag Berlin Heidelberg
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Kelem, S.H. (1994). Meaningful benchmarks for logic optimization of table-lookup FPGAs. In: Hartenstein, R.W., ServÃt, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_98
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DOI: https://doi.org/10.1007/3-540-58419-6_98
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Online ISBN: 978-3-540-48783-8
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