A systolic architecture for high speed hypergraph partitioning using a genetic algorithm

Abstract

We present a systolic array architecture to solve the problem of hypergraph partitioning. The architecture is based on a sophisticated search technique belonging to the class of genetic algorithms. A hypergraph is decomposed into a stream of fine grained, bit string data in which they are propagated into an array of locally connected processing elements. Although each processing element can handle only a few simple bit level Boolean operations, it is shown that the overall connected array forms a powerful hardware partitioning engine in which pipelining and parallelism are fully exploited. Three inner procedures in this GA based solution were parallelized, namely, the fitness evaluation, crossover and mutation operations. A time complexity analysis together with a brief logic block diagrams for the parallel architecture are presented. Simulated results indicated good speedup.