Abstract
A new Field Programmable Gate Array (FPGA) architecture is described. This architecture includes a number of novel features not found in currently available FPGAs. It is believed to offer a significantly improved logic density in some common applications.
This paper describes the development of the FPGA and looks at the mapping onto it of some interesting application circuit elements. The design is discussed in approximately chronological order which allows us to explain other options which were considered and rejected during the development process.
Formerly of Oxford Parallel, Parks Road, Oxford OX1 3QD.
This work was undertaken by Oxford Parallel, which is part of Oxford University Computing Laboratory. The work was initially funded by the Department of Trade and Industry under the Parallel Applications Programme, with the support of Inmos Limited (now part of SGS-Thomson Microelectronics Limited). Since May 1994 it has been supported by ESPRIT project P8202 (CoCo).
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References
Ian Page and Wayne Luk. “Compiling occam into Field-Programmable Gate Arrays” in “FPGAs” W.R. Moore, W. Luk (eds), Abingdon EE&CS Books, 1991
Brown, Francis, Rose and Vranesic. “Field Programmable Gate Arrays”, Kluwer Academic Publishers
Singh, Rose, Chow and Lewis. “The effects of Logic Block Architecture on FPGA Performance” in IEEE Journal of Solid State Circuits, Vol.27 No.3 (March 1992)
Lawrence et. al., “Using Reconfigurable Hardware To Speed Up Product Development And Performance” in this volume
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© 1995 Springer-Verlag Berlin Heidelberg
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Stansfield, A., Page, I. (1995). The design of a new FPGA architecture. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_93
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DOI: https://doi.org/10.1007/3-540-60294-1_93
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