Abstract
In this article we describe the theoretical foundations for the VVT-RT test system (Verification, Validation and Test for Reactive Real-Time Systems) which supports automated test generation, test execution and test evaluation for reactive systems. VVT-RT constructs and evaluates tests based on formal CSP specifications [6], making use of their representation as labelled transition systems generated by the CSP model checker FDR [3]. The present article provides a sound formal basis for the development and verification of high-quality test tools: Since, due to the high degree of automation offered by VVT-RT, human interaction becomes superfluous during critical phases of the test process, the trustworthiness of the test tool is an issue of great importance. The VVT-RT system will therefore be formally verified so that it can be certified for testing safety-critical systems. The present article represents the starting point of this verification suite, where the basic strategies for test generation and test evaluation used by the system are formally described and verified. VVT-RT has been designed to support automation of both untimed and real-time tests. The present article describes the underlying theory for the untimed case. Exploiting these results, the concepts and high-level algorithms used for the automation of real-time tests are described in a second report which is currently prepared [14]. At present, VVT-RT is applied for hardware-in-the-loop tests of railway and tramway control computers.
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Peleska, J., Siegel, M. (1996). From testing theory to test driver implementation. In: Gaudel, MC., Woodcock, J. (eds) FME'96: Industrial Benefit and Advances in Formal Methods. FME 1996. Lecture Notes in Computer Science, vol 1051. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60973-3_106
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