Abstract
Flowmap ([1]) was the first delay-optimal algorithm for the technology mapping of LUT-based FPGAs. However, even though this algorithm is polynomial, rapid prototyping using FPGAs requires faster solutions. This paper provides an efficient parallelization of flowmap that minimizes locking on shared memory architectures. The influence of scheduling strategies and technology-specific parameters on speedups is studied. The expected running time is also analyzed. The parallel algorithms yield speedups of around 4 to 5 on 8 processors.
Supported in part by the Semiconductor Research Corporation and the Joint Services Electronics Program under grants 95-DP-109 and N00014-96-1-0129 respectively.
Supported in part by the National Science Foundation under grant MIP-9222408.
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References
Cong, J., and Y. Ding, “FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,” IEEE Trans. Computer-aided Design 13 (1), January 1994, 1–13.
Banerjee, P., Parallel Algorithms for VLSI Computer-Aided Design, Prentice Hall, Inc., Englewood Cliffs, NJ, 1995.
Yang, H., and D. F. Wong, “Edge-Map: Optimal Performance Driven Technology Mapping for Iterative LUT Based FPGA Designs,” Digest IEEE Intl. Conf. on CAD, November 1994, 150–155.
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© 1996 Springer-Verlag Berlin Heidelberg
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Boppana, V., Saxena, P., Banerjee, P., Fuchs, W.K., Liu, C.L. (1996). A parallel algorithm for the technology mapping of LUT-based FPGAs. In: Bougé, L., Fraigniaud, P., Mignotte, A., Robert, Y. (eds) Euro-Par'96 Parallel Processing. Euro-Par 1996. Lecture Notes in Computer Science, vol 1123. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61626-8_109
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DOI: https://doi.org/10.1007/3-540-61626-8_109
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