Abstract
The concept of “systems on silicon” has generated great interest in system-level synthesis and associated design tools. However, the challenges of a complete automated design flow for FPGAs, allowing algorithmic exploration, architectural design and efficient implementation have not yet been met. In order to meet these challenges, the IRIS synthesis system has been developed, and this paper describes the methodology and capabilities of IRIS, and demonstrates how this tool can apply automated system-level synthesis to derive FPGA designs, and also ensure that the hardware on the device is used very efficiently at the implementation stage.
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Trainor, D.W., Woods, R.F. (1996). Architectural synthesis and efficient circuit implementation for field programmable gate arrays. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_12
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DOI: https://doi.org/10.1007/3-540-61730-2_12
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