Abstract
Exact and heuristic techniques are presented to calculate the Boolean relation for an arbitrary subcircuit in a multiple-level logic circuit with an external don’t care set. We are not restricted to process subcircuits which are only driven by primary inputs. The new techniques keep BDD sizes small and therefore allow the calculation of Boolean relations for many circuits of nontrivial size which could not be dealt with before. The efficiency of the techniques is demonstrated on various benchmark circuits. The developed techniques are applied to multiple-level logic optimization.
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© 1995 IFIP International Federation for Information Processing
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Wurth, B., Wehn, N. (1995). Multiple-Level Logic Optimization with Boolean Relations. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_2
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DOI: https://doi.org/10.1007/978-0-387-34920-6_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
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