Abstract
Functional delay fault testing is concerned with propagating a transition from a primary input to a primary output of a combinational circuit. Since it does not consider individual paths in the circuit, it can overcome the biggest limitation of path delay fault testing: the explosion in the size of fault lists. Functional delay fault testing can also be used to derive test sets for IP (Intellectual Property) circuits whose implementation details are not provided. Boolean Satisfiability (SAT) and BDDs have been widely used for a variety of EDA (Electronic Design Automation) applications. Even though there have been few experimental studies to conclude the superiority of one to the other, they have been compared for a number of specific tasks in the EDA field. In this paper we show that SAT–based functional delay fault testing can yield very competitive results with careful construction of the CNF formulas for the target faults. In particular, using simple structural analysis of the circuit formulas of minimum size can be easily generated. CNF formula construction based on the circuit consistency function is presented and experimental results for ISCAS 85 and 89 circuits are reported.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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© 2000 IFIP International Federation for Information Processing
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Kim, J., Silva, J.M., Sakallah, K.A. (2000). Satisfiability-Based Functional Delay Fault Testing. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_32
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DOI: https://doi.org/10.1007/978-0-387-35498-9_32
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