Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits

Abstract

In implementing high performance clock and data recovery (CDR) circuits, there is an interesting tradeoff offered between analog and digital circuit implementations. Analog circuits provide a relatively low power and low area approach to performing high speed, continuous-time processing of signals, but lack the ability to perform sophisticated processing tasks that demand high accuracy and repeatability. In contrast, digital circuits readily provide the ability to perform complex processing tasks with high repeatability, but can be costly in terms of power and area when high resolution is required at high speeds. A mixed-signal approach to implementation combines both analog and digital circuits (i.e., a hybrid approach) such that each performs tasks best suited to their strengths in order to accomplish the desired functionality.

In this chapter, we examine mixed-signal implementation techniques that allow the achievement of high performance CDR circuits. We do this by example, and present a 2.5 Gbit/s, fully integrated CDR in 0.25 micron CMOS that utilizes a hybrid phase-to-digital converter, loop filter, and VCO to achieve 1.4 ps of rms jitter with a compact implementation that fits within a 5 mm by 5 mm package. In addition, an all-digital frequency acquisition method is utilized which allows acquisition times less than 2 ms without the need for an external frequency reference.