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Compiling for VLIW DSPs

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Handbook of Signal Processing Systems

Abstract

This chapter describes fundamental compiler techniques for VLIW DSP processors. We begin with a review of VLIW DSP architecture concepts, as far as relevant for the compiler writer. As a case study, we consider the TI TMS320C62xTM clustered VLIW DSP processor family. We survey the main tasks of VLIW DSP code generation, discuss instruction selection, cluster assignment, instruction scheduling and register allocation in some greater detail, and present selected techniques for these, both heuristic and optimal ones. Some emphasis is put on phase ordering problems and on phase coupled and integrated code generation techniques.

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  1. Department of Computer Science (IDA), Linköping University, S-58183, Linköping, Sweden

    Christoph W. Kessler

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  1. Christoph W. Kessler
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Correspondence to Christoph W. Kessler .

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Editors and Affiliations

  1. , Dept. of Electrical and, University of Maryland, A. V. Williams Bldg. 2311, College Park, 20742, Maryland, USA

    Shuvra S. Bhattacharyya

  2. Leiden Inst. Advanced Computer Science, Leiden Embedded Research Center, Leiden University, Niels Bohrweg 1, Leiden, 2333 CA, Netherlands

    Ed F. Deprettere

  3. RWTH Aachen University, Templergraben 55, Aachen, 52056, Germany

    Rainer Leupers

  4. , Department of Computer Systems, Tampere University of Technology, Korkeakoulunkatu 1, Tampere, 33720, Finland

    Jarmo Takala

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Kessler, C.W. (2010). Compiling for VLIW DSPs. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6345-1_22

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