Abstract
Using our example system from Chapter 1, we have seen how the interconnect is dimensioned, how resources are allocated and how the resulting hardware and software is instantiated and verified. In this chapter, we take the last step and demonstrate the diversity, composability, predictability, reconfigurability and automation of our interconnect by creating an actual system instance.
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Notes
- 1.
In this chapter we do not demonstrate scalability due to the limited resources on our target FPGA.
- 2.
C-HEAP in its entirety is not only a protocol for cooperation and communication between tasks, but also a top-down design methodology and an architectural template [144].
- 3.
In fact, the parallelisation is done by master students as part of a MSc course where the proposed case study, including the interconnect, is used as part of the experimental platform [76].
- 4.
It should be noted that the processor core we use is extremely simple not optimised in any way for JPEG decoding.
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Hansson, A., Goossens, K. (2011). FPGA Case Study. In: On-Chip Interconnect with aelite. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6865-4_7
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DOI: https://doi.org/10.1007/978-1-4419-6865-4_7
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