Abstract
The novel modular special instructions (SIs) are described in Chap. 3 and the novel run-time system that dynamically determines the reconfiguration decisions to exploit the features of modular SIs is described in Chap. 4. To implement modular SIs, connect them to the core pipeline, and allow a run-time system to determine reconfiguration decision, a specialized processor architecture is needed to support these features, i.e., the RISPP architecture. In Sect. 4.1 and, in particular, in Fig. 4.1, a first overview of the RISPP architecture is given. There, it was already pointed out that it is not intended to define a completely new processor architecture. Instead, RISPP builds upon an existing architecture that is extended toward the RISPP requirements. In particular, in the scope of the presented work, a DLX core processor (created with ASIP Meister [ASI]) and later a SPARC V8 core processor (Leon2 [Aer]) were examined. This chapter focuses on the implementation details of the Leon2 prototype, although the general concepts are applicable to other architectures as well.
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Notes
- 1.
Early work was done on an Virtex-II 3000 and 6000, whereas the final prototype runs on an Virtex-4 LX 160.
- 2.
Actually, each byte is equipped with an extra parity bit that is user specific but cannot be initialized with the FPGA bitstream; thus, each BRAM provides 18 Kbit.
- 3.
Actually, the Leon 2 implements register windows, however, at most 32 registers are visible (and thus addressable) at the same time.
- 4.
Constant during compile time and run time but not during SI design time (otherwise it could be hard coded within the SI).
- 5.
Note, “RM” stands for rotation manager, indicating RISPP’s run-time system.
- 6.
Reconfigurable functional unit (RFU) corresponds to a reconfigurable region into which an SI implementation may be loaded.
- 7.
For simplicity, only six bit addresses are written and the last four bits (indicating which byte of a quad-word shall be accessed) are underlined.
- 8.
Note that atoms do not necessarily use all inputs and outputs.
- 9.
Despite providing the input from and writing back the results to the general-purpose register file.
- 10.
This means that all components within the IP core are placed and routed relative to each other, but the IP core itself can be placed at different (not necessarily all) places on the FPGA without affecting the IP-core internal composition.
- 11.
When only minor changes need to be reconfigured, then reconfiguring a single frame might be sufficient (e.g., to change a value in a LUT), however, reconfigurable modules typically cover CLB subarrays as smallest entity.
- 12.
The Xilinx Virtex series provides the feature of a so-called glitchless reconfiguration, i.e., if a configuration bit after its reconfiguration has the same value like before its reconfiguration, then it is guaranteed that this bit does not glitch in between (the Xilinx Spartan series does not provide this feature).
- 13.
Actually, the configuration is reset to the configuration of the static bitstream which might have changed since its initial configuration as a normal part of operation if, for instance, the configuration bits were used as memory using the so-called ‘distributed RAM’ IP core [Xil05a].
- 14.
In case of an unaligned access it might take longer, same if the LSU accesses the main memory instead of the on-chip scratchpad memory.
- 15.
In addition, a spare memory area is available that is used to mask EEPROM-internal errors of memory cells.
- 16.
A special flash memory type (which is a special EEPROM type) that provides faster access time and a smaller footprint in comparison to a NOR-array, but does not offer a random access on the data.
- 17.
Considering the average time to read an SRAM buffer and wait until the other buffer is filled.
- 18.
No comparisons with Virtex-4 are presented, but the Spartan-3 provides the same LUT structure than the Virtex-4 (i.e., four-input LUTs), whereas the Virtex-5 uses a redesigned structure (six-input LUTs); thus the Spartan-3 results are considered to be more significant for the presented Virtex-4 results.
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Bauer, L., Henkel, J. (2011). RISPP Architecture Details. In: Run-time Adaptation for Reconfigurable Embedded Processors. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7412-9_5
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DOI: https://doi.org/10.1007/978-1-4419-7412-9_5
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