Abstract
In the hunt to find a replacement for CMOS, material scientists are developing a wide range of nanomaterials and nanomaterial-based devices that offer significant performance improvements. One example is the carbon nanotube field-effect transistor (CNFET), which replaces the traditional silicon channel with an array of semiconducting carbon nanotubes (CNTs). Due to the increased variation and defects in nanometer-scale fabrication and the regular nature of bottom-up self-assembly, field-programmable devices are a promising initial application for such technologies. In this chapter, we detail the design and evaluation of a nanomaterial-based architecture called FPCNA (field-programmable carbon nanotube array). Nanomaterial-based devices and circuit building blocks are developed and characterized, including a lookup table created entirely from continuous CNT ribbons. To determine the performance of these building blocks, variation-aware physical design tools are used, with statistical static timing analysis (SSTA) that can handle both Gaussian and non-Gaussian random variables. When the FPCNA architecture is evaluated using this computer-aided design (CAD) flow, a 2.75× performance improvement is seen over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5.07× footprint reduction compared with a baseline FPGA.
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Acknowledgments
This work was partially supported by NSF Career Award CCF 07–46608, NSF grant CCF 07–02501, and a gift grant from Altera Corporation. We also appreciate the helpful discussions with Prof. John Rogers of the University of Illinois at Urbana Champaign and Prof. Subhasish Mitra of Stanford University.
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Dong, C., Chilstedt, S., Chen, D. (2011). FPCNA: A Carbon Nanotube-Based Programmable Architecture. In: Jha, N., Chen, D. (eds) Nanoelectronic Circuit Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7609-3_9
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DOI: https://doi.org/10.1007/978-1-4419-7609-3_9
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