Abstract
Three-dimensional (3D) stacking of ultra-thin integrated circuits (ICs) is identified as an inevitable solution for future system miniaturization and functional diversification. 3D integration offers a long list of benefits in terms of system form factor, density scaling and multiplication, reduced interconnection latency and power consumption, bandwidth enhancement, and heterogeneous integration of disparate technologies. In this 3D implementation, thinned IC layers are seamlessly bonded with a reliable bonding medium and vertically interconnected with electrical through strata via (TSV). The objective of this chapter is to discuss performance enhancement as well as new integration capabilities brought about by 3D technology, enabling technology platforms, and potential applications made possible by 3D technology.
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Acknowledgments
The author is supported by funding from the Nanyang Technological University through an award of Nanyang Assistant Professorship, Defense Science and Technology Agency (DSTA, Singapore), Semiconductor Research Corporation (SRC, USA) through a subcontract from the Interconnect and Packaging Center at the Georgia Institute of Technology, and Defense Advanced Research Projects Agency (DARPA, USA). The author thanks Professor Rafael Reif of MIT for his constructive and valuable comments on the content of this chapter.
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Tan, C. (2011). Three-Dimensional Integration of Integrated Circuits—an Introduction. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_1
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