Skip to main content

Three-Dimensional Integration of Integrated Circuits—an Introduction

  • Chapter
  • First Online:
3D Integration for NoC-based SoC Architectures

Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

Three-dimensional (3D) stacking of ultra-thin integrated circuits (ICs) is identified as an inevitable solution for future system miniaturization and functional diversification. 3D integration offers a long list of benefits in terms of system form factor, density scaling and multiplication, reduced interconnection latency and power consumption, bandwidth enhancement, and heterogeneous integration of disparate technologies. In this 3D implementation, thinned IC layers are seamlessly bonded with a reliable bonding medium and vertically interconnected with electrical through strata via (TSV). The objective of this chapter is to discuss performance enhancement as well as new integration capabilities brought about by 3D technology, enabling technology platforms, and potential applications made possible by 3D technology.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. R.P. Feynman, The Pleasure of Finding Things Out, Perseus Publishing, Cambridge, p. 28, 2000.

    Google Scholar 

  2. C.G. Hwang, New Paradigms in the Silicon Industry. In: Keynote Speech, IEDM, 2006.

    Google Scholar 

  3. Intel Corporation: http://www.intel.com

    Google Scholar 

  4. A. Khakifirooz, Transport Enhancement Techniques for Nanoscale MOSFETs. PhD Thesis, MIT, Cambridge, MA, 2008.

    Google Scholar 

  5. S. Saxena et al, Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies. IEEE Transaction on Electron Devices, 55(1), p. 131, 2008.

    Article  Google Scholar 

  6. S. Nassif et al, High Performance CMOS Variability in the 65 nm Regime and Beyond, IEDM, p. 569, 2007.

    Google Scholar 

  7. D. Sylvester and C. Hu, Analytical Modeling and Characterization of Deep-Submicrometer Interconnect. Proceedings of the IEEE, 89(5), p. 634, 2001.

    Article  Google Scholar 

  8. P. Kapur, J.P. McVittie, and K.C. Saraswat, Realistic Copper Interconnect Performance with Technological Constraints. Proceedings of the IEEE Interconnect Technology Conference, p. 233, 2001.

    Google Scholar 

  9. P.G. Emma, Is 3D Chip Technology the Next Growth Engine for Performance Improvement? IBM Journal of Research and Development, 52(6), p. 541, 2008.

    Article  Google Scholar 

  10. Tezzaron: http://www.tezzaron.com

    Google Scholar 

  11. R.E. Jones et al, Technology and Application of 3D Interconnect. Proceedings IEEE International Conference Integrated Circuit Design and Technology, p. 176, 2007.

    Google Scholar 

  12. S.K. Pozder et al, Status and Outlook. In: Wafer Level 3-D ICs Process Technology (Edited by C.S. Tan, R.J. Gutmann, and L.R. Reif), Springer, New York, p. 333, 2008.

    Google Scholar 

  13. N. Miura et al, Capacitive and Inductive-Coupling I/Os for 3D Chips. In: Integrated Interconnect Technologies for 3D Nanoelectronic Systems (Edited by M.S. Bakir and J.D. Meindl), Artech House, Boston, MA, p. 449, 2009.

    Google Scholar 

  14. S. Kawamura, N. Sasaki, T. Iwai, M. Nakano, and M. Takagi, Three-Dimensional CMOS ICs Fabricated by Using Beal Recrystallization. IEEE Electron Device Letters, 4(10), p. 366, 1983.

    Article  Google Scholar 

  15. T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, Three Dimensional ICs, Having Four Stacked Active Device Layers. In: IEDM Technical Digest, p. 837, 1989.

    Google Scholar 

  16. V. Subramanian, M. Toita, N.R. Ibrahim, S.J. Souri, and K.C. Saraswat, Low-Leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFTs for Vertical Integration Applications. IEEE Electron Device Letters, 20(7), p. 341, 1999.

    Article  Google Scholar 

  17. V.W.C. Chan, P.C.H. Chan, and M. Chan, Three-Dimensional CMOS SOI Integrated Circuit Using High-Temperature Metal-Induced Lateral Crystallization. IEEE Transaction on Electron Devices, 48(7), p. 1394, 2001.

    Article  Google Scholar 

  18. S. Pae, T. Su, J.P. Denton, and G.W. Neudeck, Multiple Layers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth. IEEE Electron Device Letters, 20(5), p. 194, 1999.

    Article  Google Scholar 

  19. B. Rajendran, R.S. Shenoy, D.J. Witte, N.S. Chokshi, R.L. DeLeon, G.S. Tompa, and R.F.W. Pease, Low Temperature Budget Processing for Sequential 3-D IC Fabrication. IEEE Transaction on Electron Devices, 54(4), p. 707, 2007.

    Article  Google Scholar 

  20. http://www.flipchips.com/tutorial71.html

    Google Scholar 

  21. M. Bohr, The New Era of Scaling in an SoC World. ISSCC, p. 23, 2009.

    Google Scholar 

  22. C.S. Tan, R.J. Gutmann, and R. Reif, Wafer Level 3-D ICs Process Technology, Springer, New York, ISBN 978-0-387-76532-7, 2008.

    Book  Google Scholar 

  23. P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Integrations: Technology and Applications of 3D Integrated Circuits, Wiley-VCH, Weinheim, ISBN 978-3-527-32034-9, 2008.

    Book  Google Scholar 

  24. A. Fan, A. Rahman, and R. Reif, Copper Wafer Bonding. Electrochemical and Solid-State Letters, 2(10), pp. 534–536, 1999.

    Article  Google Scholar 

  25. R. Tadepalli, and Carl V. Thompson, Quantitative Characterization and Process Optimization of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits. Proc. of the IEEE 2003 International Interconnect Technology Conference, pp. 36–38, 2003.

    Google Scholar 

  26. C.S. Tan, K.N. Chen, A. Fan, and R. Reif, The Effect of Forming Gas Anneal on the Oxygen Content in Bonded Cu Layer. Journal of Electronic Materials, 34(12), pp. 1598–1602, 2005.

    Article  Google Scholar 

  27. K.N. Chen, A. Fan, C.S. Tan, and R. Reif, Temperature and Duration Effect on Microstructure Evolution During Copper Wafer Bonding. Journal of Electronic Materials, 32(12), pp. 1371–1374, 2003.

    Article  Google Scholar 

  28. K.N. Chen, C.S. Tan, A. Fan, and R. Reif, Morphology and Bond Strength of Copper Wafer Bonding. Electrochemical and Solid-State Letters, 7(1), pp. G14–G16, 2004.

    Article  Google Scholar 

  29. C.S. Tan, R. Reif, D. Theodore, and S. Pozder, Observation of Interfacial Voids Formation in Bonded Copper Layer. Applied Physics Letters, 87(20), p. 201909, 2005.

    Article  Google Scholar 

  30. C.S. Tan, K.N. Chen, A. Fan, R. Reif, and A. Chandrakasan, Silicon Layer Stacking Enabled by Wafer Bonding. MRS Symposium Proceedings, 970, pp. 193–204, 2007.

    Google Scholar 

  31. A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, S. Pargfrieder, B. Swinnen, and E. Beyne, Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs. Proceedings of IEEE International Interconnect Technology Conference, pp. 207–209, 2007.

    Google Scholar 

  32. R.J. Gutmann, J.J. McMahon, and J.-Q. Lu, Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers. Materials Research Society Symposium Proceedings, 970, pp. 205–214, 2007.

    Google Scholar 

  33. P. Enquist, High Density Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications. Materials Research Society Symposium Proceedings, 970, pp. 13–24, 2007.

    Google Scholar 

  34. T.H. Kim, M.M.R. Howlader, T. Itoh, and T. Suga, Room Temperature Cu-Cu Direct Bonding Using Surface Activated Bonding Method. Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films, 21(2), pp. 449–453, 2003.

    Article  Google Scholar 

  35. R. Tadepalli and Carl V. Thompson, Formation of Cu-Cu Interfaces with Ideal Adhesive Strengths via Room Temperature Pressure Bonding in Ultrahigh Vacuum, Appl. Phys. Lett., 90, p. 151919, 2007.

    Article  Google Scholar 

  36. P.-I. Wang, T. Karabacak, J. Yu, H.-F. Li, G.G. Pethuraja, S.H. Lee, M.Z. Liu, and T.-M. Lu, Low Temperature Copper-Nanorod Bonding for 3D Integration. Materials Research Society Symposium Proceedings, 970, pp. 225–230, 2007.

    Google Scholar 

  37. P. Benkart, A. Kaiser, A. Munding, M. Bschorr, H.-J. Pfleiderer, E. Kohn, A. Heittmann, and U. Ramacher, 3D Chip Stack Technology using Through-Chip Interconnects. IEEE Design & Test of Computers, 22(6), pp. 512–518, 2005.

    Article  Google Scholar 

  38. P. Gueguen, L. Di Cioccio, M. Rivoire, D. Scevola, M. Zussy, A.M. Charvet, L. Bally, and L. Clavelier, Copper Direct Bonding for 3D Integration. IEEE International Interconnect Technology Conference, pp. 61–63, 2008.

    Google Scholar 

  39. T. Osborn, A. He, H. Lightsey, and P. Kohl, All-Copper Chip-to-Substrate Interconnects. Proceedings of IEEE Electronic Components and Technology Conference, pp. 67–74, 2008.

    Google Scholar 

  40. D.F. Lim, S.G. Singh, X.F. Ang, J. Wei, C.M. Ng, and C.S. Tan, Achieving Low Temperature Cu to Cu Diffusion Bonding with Self Assembly Monolayer (SAM) Passivation. IEEE International Conference on 3D System Integration, art. no. 5306545, 2009.

    Google Scholar 

  41. D.F. Lim, S.G. Singh, X.F. Ang, J. Wei, C.M. Ng, and C.S. Tan, Application of Self Assembly Monolayer (SAM) in Cu-Cu Bonding Enhancement at Low Temperature for 3-D Integration. Advanced Metallization Conference, Baltimore, October 13–15, 2009. In: D.C. Edelstein and S.E. Schulz (Eds), AMC 2009, pp. 259–266, Materials Research Society, 2010.

    Google Scholar 

  42. C.S. Tan, D.F. Lim, S.G. Singh, S.K. Goulet, and M. Bergkvist, Cu-Cu Diffusion Bonding Enhancement at Low Temperature by Surface Passivation using Self-assembled Monolayer of Alkane-Thiol. Applied Physics Letters, 95(19), p. 192108, 2009.

    Article  Google Scholar 

  43. D.F. Lim, J. Wei, C.M. Ng, and C.S. Tan, Low Temperature Bump-less Cu-Cu Bonding Enhancement with Self Assembled Monolayer (SAM) Passivation for 3-D Integration. IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, June 1–4, pp. 1364–1369, 2010.

    Google Scholar 

Download references

Acknowledgments

The author is supported by funding from the Nanyang Technological University through an award of Nanyang Assistant Professorship, Defense Science and Technology Agency (DSTA, Singapore), Semiconductor Research Corporation (SRC, USA) through a subcontract from the Interconnect and Packaging Center at the Georgia Institute of Technology, and Defense Advanced Research Projects Agency (DARPA, USA). The author thanks Professor Rafael Reif of MIT for his constructive and valuable comments on the content of this chapter.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Chuan Seng Tan .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Tan, C. (2011). Three-Dimensional Integration of Integrated Circuits—an Introduction. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-7618-5_1

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-7617-8

  • Online ISBN: 978-1-4419-7618-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics