Abstract
This chapter discusses the challenges and opportunities of verifying RTL designs. In particular, we explore the opportunities presented by our proposed design approach. This approach – encapsulating the sequential code in a single state machine and combinational code in a set of functions – allows us to develop some powerful module level verification techniques. These techniques get us closer to a complete verification strategy than is possible using traditional design and coding practices.
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© 2011 Synopsys, Inc.
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Keating, M. (2011). Verification. In: The Simple Art of SoC Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8586-6_6
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DOI: https://doi.org/10.1007/978-1-4419-8586-6_6
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-8585-9
Online ISBN: 978-1-4419-8586-6
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