Abstract
Timing Analysis of an ASIC design used to be traditionally done through simulation . The process involved applying a set of vectors and checking if the various signals are available at the desired time – at various points in the design. However, this process was too much dependent on the designer’s coverage of the test-vectors. Hence, there was always a risk of missing some vector– which will actually not meet the timing and can result in failure to achieve the desired frequency. With increasing chip complexities, it became almost impossible to ensuring a complete and exhaustive coverage of vectors.
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Notes
- 1.
Note, the use of the phrase, “seems to be correct”. This is because, in simulation, you are validating the design against the vectors that have been applied, but, there is no guarantee that the vectors have been applied for all possible cases. Hence, there is a possibility that the design might fail for a situation – for which the vectors were not applied.
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© 2011 Springer Science+Business Media, LLC
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Churiwala, S., Garg, S. (2011). Timing Analysis. In: Principles of VLSI RTL Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9296-3_3
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DOI: https://doi.org/10.1007/978-1-4419-9296-3_3
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