Abstract
This chapter considers the number of gates to realize logic functions by OR-AND-OR three-level networks under the condition that both true and complemented variables are available, and each gate has no fan-in and fan-out constraints. We show that an arbitrary n-variable function can be realized by an OR-AND-OR three-level network with at most 2r+1 + 1 gates, where n = 2r and r is an integer. We also prove that for sufficiently large r, regardless of the number of levels, we need at least 2r+1 (1 - ξ) gates to realize almost all functions of n variables by an AND-OR multi-level network, where ξ is an arbitrarily small positive real number (0 < ξ < 1). We developed a heuristic algorithm to design OR-AND-OR three-level networks, realized various functions, and compared the number of gates for OR-AND-OR three-level networks with AND-OR two-level ones. For arithmetic functions of 8 variables, three-level networks require, on the average, 40% fewer gates than AND-OR two-level ones. For other benchmark functions of 9 to 128 variables, three-level networks required up to 91% fewer gates. For randomly generated functions of 10 variables, three-level networks required 50% fewer gates.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
B. Brustmann and I. Wegener, “The complexity of symmetric functions in bounded-depth circuits,” Information Processing Letters 25, pp. 217–219, 1987.
J. N. Culliney, M. H. Young, T. Nakagawa, and S. Muroga, “Results of the synthesis of optimal networks of AND and OR gates for four-variable switching functions,” IEEE Trans. on Comput., Vol. C-27, No. 1, pp. 76–85, Jan. 1979.
J. T. Hastad, Computational Limitations for Small-Depth Circuits, The MIT Press, Cambridge, 1989.
M. Karpovsky, “Multilevel logical networks,” IEEE Trans. on Comput., Vol. C-36, No. 2, pp. 215–226, Feb. 1987.
E. L. Lawler, “An approach to multilevel Boolean minimization,” Journal of ACM, Vol. 11, No. 3, pp. 283–295, July 1964.
E. J. McCluskey, Introduction to the Theory of Switching Circuits, McGraw-Hill, 1965.
D. E. Muller, “Complexity in electronic switching circuits,” IRE Trans. Elec. Computers, EC-5, 1, pp. 15–19, 1956.
C. A. Papachristou, “Characteristic measure of switching functions,” Information Sciences, 13, pp. 51–75, 1977.
T. Sasao, “Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays,” IEEE Trans. Comput., Vol. C-30, pp. 635–643, Sept. 1981.
T. Sasao, “Input variable assignment and output phase optimization of PLA’s,” IEEE Trans. Comput., Vol. C-33, No. 10, pp. 879–894, Oct. 1984.
T. Sasao and M. Higashida, “A design method for three-level logic circuits,” (in Japanese), The Technical Papers of IEICE Japan, VLD88–84, Dec. 1988.
T. Sasao, “On the complexity of networks realized by fiber-optic logic elements,” SPIE’s Technical Symposium on High Power Lasers and Optical Computing, Conference 1215, Los Angeles, Jan. 17, 1990 (invited talk).
J. E. Savage, The Complexity of Computing, John Wiley & Sons, 1976.
C. E. Shannon, “The synthesis of two-terminal switching circuits,” Bell Syst. Tech. J. 28, 1, pp. 59–98, 1949.
Signetics, Designing with Programmable Macro Logic, 1987.
İ. Wegener, The Complexity of Boolean Functions, John Wiley & Sons, Stuttgart, 1987.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1996 Kluwer Academic Publishers
About this chapter
Cite this chapter
Sasao, T. (1996). Or-and-Or Three-Level Networks. In: Sasao, T., Fujita, M. (eds) Representations of Discrete Functions. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1385-4_13
Download citation
DOI: https://doi.org/10.1007/978-1-4613-1385-4_13
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8599-1
Online ISBN: 978-1-4613-1385-4
eBook Packages: Springer Book Archive