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Introduction

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Models for Large Integrated Circuits

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 103))

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Abstract

The aim of integrated circuit design is often to assemble as many devices as possible in a chip of silicon together with all the interconnects and driver circuits needed. Present day technology allows feature resolution in the neighborhood of 1 micron (=10−6m), moving downward to possibly 0.5 micron in the mid nineties. Very small device dimensions and proximity can be achieved resulting in high packing densities and “Ultra Large Scale Integration”. In addition to lateral size reduction, modern technology offers an increasing number of interconnect layers, starting from straps between the polysilicon interconnect layers and the so called “diffusion” paths in the silicon substrate, metal 1, metal 2 and possibly higher metal layers. This stacking of layers is made possible by advanced techniques of planarization.

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References

  1. V.M. Adamjan, D.Z. Arov, and M.G. Krein, “Analytic Properties of Schmidt Pairs for a Hankel Operator and the Schur-Takagi Problem,” Math. USSR Sbornik 15(1) pp. 31–73 (1971).

    Article  Google Scholar 

  2. W.L. Engl, H.K. Dirks, and B. Meinerzhagen, “Device Modeling,” Proc. of The IEEE 71(1) pp. 10–32 (Jan. 1983).

    Article  Google Scholar 

  3. S. Selberherr, A. Schutz, and H. W. Potzl, “MINIMOS—A Two-Dimensional MOS Transistor Analyzer,” IEEE Transactions on Electron Devices ED-27(8) pp. 1540–1550 (August 1980).

    Article  Google Scholar 

  4. L.D. Yau, “A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET’s,” Solid-State Electronics 17 pp. 1059–1063 (1974).

    Article  Google Scholar 

  5. P.S. Lin and C.Y. Wu, “A New Approach to Analytically Solving the Two-Dimensional Poisson’s Equation and Its Application in Short-Channel MOSFET Modeling,” IEEE Transaction on Electron Devices ED-34(9) pp. 1947–1956 (Sept. 1987).

    Google Scholar 

  6. J.E. Meyer, “MOS models and circuit simulation,” RCA review 32 pp. 42–63 (March 1971).

    Google Scholar 

  7. D.E. Ward and R.W. Dutton, “A Charge-Oriented Model for MOS Transistor Capacitances,” IEEE J. Solid-State Circuits SC-13(5) pp. 703–707 (Oct. 1978).

    Article  Google Scholar 

  8. L.M. Dang, “A Simple Current Model for Short-Channel IGFET and Its Application to Circuit Simulation,” IEEE J. Solid-State Circuits SC-14(2) pp. 358–367 (April 1979).

    Google Scholar 

  9. G. Merckel, “A Simple Model of the Threshold Voltage of Short and Narrow Channel MOSFET’s,” Solid-State Electronics 23 pp. 1207–1213 (1980).

    Article  Google Scholar 

  10. G.W. Taylor, “The effects of Two-Dimensional Charge Sharing on the Above-Threshold Characteristics of Short-Channel IGFETs,” Solid-State Electronics 22 pp. 701–717 (1979).

    Article  Google Scholar 

  11. P.K. Chatterjee, P. Yang, and H. Shichijo, “Modelling of small MOS devices and device limits,” IEEE PROC. 130, pt. I(3) pp. 105–125 (June 1983).

    Google Scholar 

  12. R.R. Troutman, “Ion-Implanted Threshold Tailoring for Insulated Gate Field-Effect Transistors,” IEEE Transactions on Electron Devices ED-24(3) pp. 182–192 (March 1977).

    Article  Google Scholar 

  13. G. Doucet and F. Van De Wiele, “Threshold Voltage of Nonuniformly Doped MOS Structures,” Solid-State Electronics 16 pp. 417–423 (1973).

    Article  Google Scholar 

  14. P. Yang and P.K. Chatterjee, “SPICE Modeling for Small Geometry MOSFET Circuits,” IEEE Transactions on CAD of integrated circuits and systems CAD-1(4) pp. 169–182 (October 1982).

    Article  Google Scholar 

  15. L.A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits. 1985.

    Google Scholar 

  16. P.K. Chatterjee, J.E. Leiss, and G.W. Taylor, “A Dynamic Average Model for the Body Effect in Ion Implanted Short Channel (L = 1 um) MOSFET’s,” IEEE Transactions on Electron Devices ED-28(5) pp. 606–607 (May 1981).

    Article  Google Scholar 

  17. P. Ratnam and C. Andre T. Salama, “A New Approach to the Modeling of Nonuniformly Doped Short-Channel MOSFET’s,” IEEE Transactions on Electron Devices ED-31(9) pp. 1289–1298 (Sept. 1984).

    Article  Google Scholar 

  18. C.Y. Wu G.S. Huang H.H. Chen F.C. Tseng and C.T. Shin “An Accurate and Analytic Threshold-tage Model for Small-Geometry MOSFETS with Single-Channel Ion Implantation in VLSI” Solid-State Electronics 28(12) pp. 1263–1269 1985.

    Article  Google Scholar 

  19. T. Toyabe and S. Asai, “Analytical Models of Threshold Voltage and Breakdown Voltage of Short-Channel MOSFET’s Derived from Two-Dimensional Analysis,” IEEE Transaction on Electron Devices ED-26(4) pp. 453–461 (April. 1979).

    Article  Google Scholar 

  20. K.N. Ratnakumar and J.D. Meindl, “Short-Channel MOST Threshold Voltage Model,” IEEE J. Solid-State Circuits SC-17(5) pp. 937–948 (Oct. 1982).

    Article  Google Scholar 

  21. D.R. Poole and D.L. Kwong, “Two-Dimensional Analytical Modeling of Threshold Voltage of Short-Channel MOSFET’s,” IEEE Electron Device Letters EDL-5(ll)pp. 443–446 (Nov. 1984).

    Article  Google Scholar 

  22. J.R. Pfiester, J.D. Shott, and J.D. Meindl, “Performance Limits of CMOS ULSI,” IEEE Transaction on Electron Devices ED-32(2)(Feb. 1985).

    Google Scholar 

  23. Z.Q. Ning, P. Dewilde, and F.L. Neerhoff, “A New Approach to Analytically Solving the 2D Poisson Equation in MOSFET,” Voortgang IOP-IC Modelleringsprojekten, Delft Univ. of Techn. The Netherlands, (Sept. 8, 1988).

    Google Scholar 

  24. S.E. Laux, “Accuracy of an effective channel length/external resistance extraction algorithm for MOSFET’s,” IEEE Transactions on Electron Devices ED-31(9) pp. 1245–1251 (Sept. 1984).

    Article  Google Scholar 

  25. B.J. Sheu, W.J. Hsu, and P.K. Ko, “An MOS Transistor Charge Model for VLSI Design,” IEEE Trans. CAD of Integrated Circuits and Systems 7(4) pp. 520–527 (April, 1988).

    Article  Google Scholar 

  26. H.B. Bakoglu and J.D. Meindl, “Optimal Interconnection Circuits for VLSI,” IEEE Trans. Electron Devices ED-32(5)(May 1985).

    Google Scholar 

  27. Network Theory Section, “Cooperative Development of An Integrated, Hierarchical and Multiview VLSI-Design System with Distributed Management on Workstations,” Internal Report, Delft Univ. of Technology, (1985).

    Google Scholar 

  28. A.E. Ruehli and P.A. Brennan, “Accurate Metallization Capacitances for Integrated Circuits and Packages,” IEEE J.Solid-State Circuits SC-8 pp. 298–290 (Aug. 1973).

    Google Scholar 

  29. Z.Q. Ning, “On the Parasitic Capacitances of VLSI Interconnections,” The ninth CAVE Workshop, (May 24–27, 1987).

    Google Scholar 

  30. Z.Q. Ning and P. Dewilde, “SPIDER: Capacitance Modelling for VLSI Interconnections,” IEEE Trans. CAD of Integrated Circuits and Systems 7(12) pp. 1221–1228 (December, 1988).

    Article  Google Scholar 

  31. W.H. Dierking and J.D. Bastian, “VLSI Parasitic Capacitance Determination by Flux Tubes,” IEEE Circuits and Systems Magazine, pp. 11–18 (March 1982).

    Google Scholar 

  32. Z.Q. Ning, P.M. Dewilde, and F.L. Neerhoff, “Capacitance Coefficients for VLSI Multilevel Metallization Lines,” IEEE Transactions on Electron Devices ED-34(3) pp. 644–649 (March 1987).

    Article  Google Scholar 

  33. J. Rubinstein, P. Penfield, JR., and M.A. Horowitz, “Signal Delay in RC Tree Networks,” IEEE Trans. Computer-Aided Design CAD-2(3) pp. 202–211 (1983).

    Article  Google Scholar 

  34. S.P. McCormick, “EXCL: A Circuit Extractor for IC Designs,” 21st Design Automation Conference Proceedings, (1984).

    Google Scholar 

  35. D.W. Kammler, “Calculation of Characteristic Admittances and Coupling Coefficients for Strip Transmission Lines,” IEEE Trans. Microwave Theory Tech. MTT-16(11) pp. 925–927 (Nov. 1968).

    Article  Google Scholar 

  36. W.T. Weeks, “Calculation of Coefficients of Capacitance of Multiconductor Transmission Lines in the Presence of a Dielectric Interface,” IEEE Trans. Microwave Theory Tech. MTT-18(l)(Jan. 1970).

    Google Scholar 

  37. P.D. Patel, “Calculation of Capacitance Coefficients for a System of Irregular Finite Conductors on a Dielectric Sheet,” IEEE Trans. Microwave Theory Tech. MTT 19(11) pp. 862–869 (Nov. 1971).

    Article  Google Scholar 

  38. P. Balaban, “Calculation of the Capacitance Coefficients of Planar Conductors on a Dielectric Surface,” IEEE Trans. Circuit Theory CT-20 pp. 725–731 (Nov. 1973).

    Google Scholar 

  39. A.E. Ruehli and P.A. Brennan, “Efficient Capacitance Calculations for Three-Dimensional Multiconductor Systems,” IEEE Trans. Microwave Theory Tech. MTT(Feb. 1973).

    Google Scholar 

  40. C.D. Taylor, G.N. Elkhouli, and T.E. Wade, “On the Parasitic Capacitances of Multilevel Parallel Metallization Lines,” IEEE Transactions on Electron Devices ED-32(ll)pp. 2408–2414 (Nov. 1985).

    Article  Google Scholar 

  41. P.E. Cottrell, E.M. Buturla, and D.R. Thomas, “Multi-Dimensional Simulation of VLSI Wiring Capacitance,” IEDM Tech. Dig., pp. 548–551 (1982).

    Google Scholar 

  42. A.H. Zemanian, “A Finite-Difference Procedure for the Exterior Problem Inherent in Capacitance Computations for VLSI Interconnections,” IEEE Trans. Electron Devices 35 (7) pp. 985–992 (July, 1988).

    Article  MathSciNet  Google Scholar 

  43. W.H. Chang, “Analytical IC Metal-Line Capacitance Formulas,” IEEE Trans. Microwave Theory Tech. MTT-24 pp. 608–611 (Sept. 1976).

    Article  Google Scholar 

  44. M.I. Elmasry, “Capacitance Calculations in MOSFET VLSI,” IEEE Electron Device Lett. EDL-3 pp. 6–7 (1982).

    Article  Google Scholar 

  45. T. Sakurai and K. Tamaru, “Simple Formulas for Two-and Three-Dimensional Capacitances,” IEEE Trans. Electron Devices ED-30 pp. 183–185 (Feb. 1983).

    Article  Google Scholar 

  46. S.G. Mikhlin and K.L. Smolitskiy, Approximate Methods for Solution of Differential and Integral Equations, American Elsevier Publishing Company Inc., New York (1967).

    MATH  Google Scholar 

  47. O.C. Zienkiewicz and K. Morgan, Finite Elements and Approximation, John Wiley & Sons (1983).

    Google Scholar 

  48. P. Silvester and R.L. Ferrari, Finite Element for Electrical Engineers, Cambridge University Press (1983).

    Google Scholar 

  49. P. Benedek, “Capacitances of a Planar Multiconductor Configuration on a Dielectric Substrate by a Mixed Order Finite-Element Method,” IEEE Trans. Circuits and Systems CAS-23(5) pp. 279–284 (May 1976).

    Article  Google Scholar 

  50. Z.Q. Ning and P. Dewilde, “An Efficient Modelling Technique for Computing the Parasitic Capacitances in VLSI Circuits,” IEEE ISC AS Proceedings 2 pp. 1131–1134 (June 7–9, 1988).

    Google Scholar 

  51. P. Dewilde and Ed.F. Deprettere, “Approximative Inversion of Positive Matrices with Applications to Modelling,” NATO ASI Series F34 pp. 211–237 (19871).

    MathSciNet  Google Scholar 

  52. P. Dewilde, “New Algebraic Methods for Modelling Large Scale Integrated Circuits,” International Journal of Circuit Theory and Applications 16 pp. 437–503 (1988).

    Article  Google Scholar 

  53. G. Strang, Linear Algebra and Its Applications, Academic Press, Inc. (1976).

    Google Scholar 

  54. I. Stakgold, Boundary Value Problems of Mathematical Physics, New York: Macmillan (1968).

    MATH  Google Scholar 

  55. A.T. de Hoop, Theorie van het Elektromagnetische Veld, Delft University Press, Delft, The Netherlands (1975).

    Google Scholar 

  56. K. Yosida, Functional Analysis, Springer-Verlag New York Inc. (1968).

    Google Scholar 

  57. L. Schwartz, Theorie des Distributions, Hermaan, Paris (1950).

    MATH  Google Scholar 

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Authors and Affiliations

  1. Delft University of Technology, Netherlands

    Patrick Dewilde & Zhen-Qui Ning

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  1. Patrick Dewilde
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  2. Zhen-Qui Ning
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© 1990 Kluwer Academic Publishers

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Dewilde, P., Ning, ZQ. (1990). Introduction. In: Models for Large Integrated Circuits. The Kluwer International Series in Engineering and Computer Science, vol 103. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1555-1_1

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  • DOI: https://doi.org/10.1007/978-1-4613-1555-1_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8833-6

  • Online ISBN: 978-1-4613-1555-1

  • eBook Packages: Springer Book Archive

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