Characterization of Unijunction Transistors Fabricated on NTD-Silicon

Abstract

The vertical planar diffused unijunction transistor (UJT) has two commonly referenced D.C. electrical parameters which can be employed to indicate local homogenity of impurity doping in silicon substrates. Specifically these parameters are: interbase resistance, which is a spreading resistance from a small diffused layer, and intrinisic standoff ratio. The first parameter, interbase resistance depends primarily on local silicon resistivity in the finished wafer, and diffusion geometry. The second parameter, intrinsic standoff ratio, depends primarily on diffusion geometry, so that local resistivity is easily obtainable from measurements of interbase resistance and intrinsic standoff ratio. Results of these measurements are presented, and are shown to point out fundamental differences between neutron transmutation doped (NTD) and float zone processed (FZ) silicon in the resistivity range of 50 to 70 ohm’cm. It is also presented how measurements of these parameters have, in turn, been used to improve the design and electrical yield of these devices, in particular, with the adaptation of the process to NTD silicon.

A review of various electrostatic models for spreading resistance is presented. The results are compared to results obtained using a three-dimensional electrolytic tank apparatus with a surface voltage probe to simulate the electric field in a chip geometry.

Devices fabricated from NTD silicon and FZ silicon are compared on the basis of local impurity doping homogeneity by the method given in this paper. The results indicate unmistakable advantages in control of parameters are obtainable from NTD silicon. These results show substantial agreement between the parametric determinations of local resistivity on finished UJT wafers and local resistivity measurements made with a spreading resistance probe. This strong correlation suggests the effects of doping inhomogeneity on some primary electrical parameters are still present after wafer processing.