Circuit Techniques for PVT Variation Tolerance

Abstract

As part of an IC, on-chip interconnects experience two types of variations: physical and environmental. A physical variation is due to the manufacturing process imperfections. Whereas, environmental variations occur during the operation of a circuit and includes dynamic variations in the supply VT. Precise control of the manufacturing process is worsening with technology scaling due to smaller dimensions, smaller number of doping atoms and aggressive lithographic techniques. This becomes a major concern since it causes uncertainty in electrical characteristics of devices and interconnecting wires which consequently affect the reliability of the system. Variability in the operating environment also affects the reliability of on-chip interconnects. As the variations increase, techniques which reduce their impacts while providing the highest performance for a given power constraint are necessary at the system, architecture, and circuit levels [116]. In this chapter, circuit level techniques which ensure signal integrity of a current sensing on-chip interconnect in the presence of PVT variations are developed and implemented. Since all the interconnects that are presented are delay-insensitive, the developed signal integrity technique considers only the signal amplitude variation.