Applying Verification Collaterals for Accurate Power Estimation

Abstract

In this chapter, we present a methodology for accurate power estimation at high-level, which utilizes the existing verification or validation resources in the design flow. This methodology can help in developing an infrastructure to estimate the power consumption at higher-level. Current power estimation methods are limited to RTL or lower level, in our approach we utilize best from both the worlds (RTL and high-level) and try to get the RTL like accuracy using high-level simulation only. We provide steps, examples of different properties using assertions, and methods to create directed testbenches as verification resources in the design flow for power estimation purpose. The approach presented in this chapter is specific to a high-level synthesis framework. We use Esterel Studio and Power Theater (to show the efficacy of our results). Our case study is performed on a finite state machine (FSM) based design. This case study presents detailed description of properties to generate the directed testbench for reaching a particular state of the FSM. Once we have the stimulus for the particular state of the FSM, we estimate the power of that particular state of the design at RTL, which is further utilized for the high-level power estimation.