Skip to main content
SpringerLink
Log in

Decidable Dataflow Models for Signal Processing: Synchronous Dataflow and Its Extensions

  • Chapter
  • First Online:
Handbook of Signal Processing Systems

Abstract

Digital signal processing algorithms can be naturally represented by a dataflow graph where nodes represent function blocks and arcs represent the data dependency between nodes. Among various dataflow models, decidable dataflow models have restricted semantics so that we can determine the execution order of nodes at compile-time and decide if the program has the possibility of buffer overflow or deadlock. In this chapter, we explain the synchronous dataflow (SDF) model as the pioneering and representative decidable dataflow model and its decidability focusing on how the static scheduling decision can be made. In addition the cyclo-static dataflow model and a few other extended models are briefly introduced to show how they overcome the limitations of the SDF model.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 219.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 279.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Ade, M., Lauwereins, R., Peperstraete, J.A.: Implementing DSP applications on heterogeneous targets using minimal size data buffers. In: Proceedings of RSP’96, pp. 166–172 (1996)

    Google Scholar 

  2. Bhattacharyya, S.S., Murthy, P.K., Lee, E.A.: Software Synthesis from Dataflow Graphs. Kluwer Academic Publisher, Norwell MA (1996)

    Book  MATH  Google Scholar 

  3. Bhattacharyya, S.S., Murthy, P.K., Lee, E.A.: APGAN and RPMC: Complementary heuristics for translating DSP block diagrams into efficient software implementations. Journal of Design Automation for Embedded Systems 2, 33–60 (1997)

    Article  Google Scholar 

  4. Bilsen, G., Engles, M., Lauwereins, R., Peperstraete, J.A.: Cyclo-static dataflow. IEEE Trans. Signal Processing 44, 397–408 (1996)

    Article  Google Scholar 

  5. Buck, J.T., Ha, S., Lee, E.A., Messerschimitt, D.G.: Ptolemy: A framework for simulating and prototyping heterogeneous systems. Int. Journal of Computer Simulation, Special issue on Simulation Software Development 4, 155–182 (1994)

    Google Scholar 

  6. Dennis, J.B.: Dataflow supercomputers. IEEE Computer Magazine 13 (1980)

    Google Scholar 

  7. Govindarajan, R., Gao, G., Desai, P.: Minimizing memory requirements in rate-optimal schedules. In: Proceedings of the International Conference on Application Specific Array Processors, pp. 75–86 (1993)

    Google Scholar 

  8. Hoang, P.D., Rabaey, J.M.: Scheduling of DSP programs onto multiprocessors for maximum throughput. IEEE Transactions on Signal Processing pp. 2225–2235 (1993)

    Google Scholar 

  9. Jung, H., Yang, H., Ha, S.: Optimized RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. Journal of Signal Processing Systems 52, 13–34 (2008)

    Article  Google Scholar 

  10. Kim, J., Shin, T., Ha, S., Oh, H.: Resource minimized static mapping and dynamic scheduling of SDF graphs. In: ESTIMedia (2011)

    Google Scholar 

  11. Lauwereins, R., Engels, M., Peperstraete, J.A., Steegmans, E., Ginderdeuren, J.V.: GRAPE: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine 7, 32–43 (1990)

    Article  Google Scholar 

  12. Lee, E.A., Messerschmitt, D.G.: Static scheduling of synchronous dataflow programs for digital signal processing. IEEE Transactions on Computer C-36, 24–35 (1987)

    Article  Google Scholar 

  13. Oh, H., Ha, S.: Memory-optimized software synthesis from dataflow program graphs with large size data samples. EURASIP Journal on Applied Signal Processing 2003, 514–529 (2003)

    Article  MATH  Google Scholar 

  14. Oh, H., Ha, S.: Fractional rate dataflow model for memory efficient synthesis. Journal of VLSI Signal Processing 37, 41–51 (2004)

    Article  Google Scholar 

  15. Parhi, K.K., Chen, Y.: Signal flow graphs and data flow graphs. In: S.S. Bhattacharyya, E.F. Deprettere, R. Leupers, J. Takala (eds.) Handbook of Signal Processing Systems, second edn. Springer (2013)

    Google Scholar 

  16. Park, C., Chung, J., Ha, S.: Extended synchronous dataflow for efficient DSP system prototyping. Design Automation for Embedded Systems 3, 295–322 (2002)

    Article  Google Scholar 

  17. Pino, J., Ha, S., Lee, E.A., Buck, J.T.: Software synthesis for DSP using Ptolemy. Journal of VLSI Signal Processing 9, 7–21 (1995)

    Article  Google Scholar 

  18. Ritz, S., Pankert, M., Meyr, H.: High level software synthesis for signal processing systems. In: Proceedings of the International Conference on Application Specific Array Processors (1992)

    Google Scholar 

  19. Ritz, S., Willems, M., Meyr, H.: Scheduling for optimum data memory compaction in block diagram oriented software synthesis. In: Proceedings of the ICASSP 95 (1995)

    Google Scholar 

  20. S. Stuijk, T.B., Geilen, M.C.W., Corporaal, H.: Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs. In: DAC, pp. 777–782 (2007)

    Google Scholar 

  21. Stuijk, S., Geilen, M.C.W., Basten, T.: Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. In: DAC, pp. 899–904 (2006)

    Google Scholar 

  22. Sung, W., Ha, S.: Memory efficient software synthesis using mixed coding style from dataflow graph. IEEE Transactions on VLSI Systems 8, 522–526 (2000)

    Article  Google Scholar 

  23. Woods, R.: Mapping decidable signal processing graphs into FPGA implementations. In: S.S. Bhattacharyya, E.F. Deprettere, R. Leupers, J. Takala (eds.) Handbook of Signal Processing Systems, second edn. Springer (2013)

    Google Scholar 

  24. Yang, H., Ha, S.: Pipelined data parallel task mapping/scheduling technique for MPSoC. In: DATE (Design Automation and Test in Europe) (2009)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Seoul National University, Seoul, Korea

    Soonhoi Ha

  2. Hanyang University, Seoul, Korea

    Hyunok Oh

Authors
  1. Soonhoi Ha
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Hyunok Oh
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Soonhoi Ha .

Editor information

Editors and Affiliations

  1. , Dept. of Electrical and, University of Maryland, A. V. Williams Bldg. 2311, College Park, 20742, Maryland, USA

    Shuvra S. Bhattacharyya

  2. Leiden Inst. Advanced Computer Science, Leiden Embedded Research Center, Leiden University, Niels Bohrweg 1, Leiden, 2333 CA, Netherlands

    Ed F. Deprettere

  3. Software for Systems on Silicon, RWTH Aachen University, Templergraben 55, Aachen, 52056, Germany

    Rainer Leupers

  4. , Department of Pervasive Computing, Tampere University of Technology, Korkeakoulunkatu 1, Tampere, 33720, Finland

    Jarmo Takala

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Ha, S., Oh, H. (2013). Decidable Dataflow Models for Signal Processing: Synchronous Dataflow and Its Extensions. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_33

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-6859-2_33

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-6858-5

  • Online ISBN: 978-1-4614-6859-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation