Skip to main content
SpringerLink
Log in

The Future of Logic Synthesis and Verification

  • Chapter
Logic Synthesis and Verification

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 654))

Abstract

Logic synthesis has been worked on for at least 40 years, and much has been accomplished, with many commercial tools developed and used pervasively. However, in light of the continual progress made in technology, more complex designs will be made and along with increased physical interactions, these will present new challenges for both synthesis and verification. We discuss some areas where these problems will arise and pose some challenges for the future.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. S. Yamashita, H. Sawada, and A. Nagoya, “A new method to express functional permissibilities for LUT based FPGAs and its applications,” in Int. Conf on CAD, pp. 254–261, Nov. 1996.

    Google Scholar 

  2. R. K. Brayton, “Understanding SPFDs: A new method for specifying flexibility,” in Int. Workshop on Logic Synthesis, 1997.

    Google Scholar 

  3. S. Sinha and R. K. Brayton, “Implementation and use of SPFDs,” in Int. Conf. on CAD, pp. 103–110, 1998.

    Google Scholar 

  4. S. Sinha and R. K. Brayton, “Robust and efficient SPFD calculations,” in Int. Workshop on Logic Synthesis, pp. 156–161, 2001.

    Google Scholar 

  5. K. T. Cheng and L. A. Entrena, “Multi-level logic optimization by redundancy addition and removal,” in European Conf. on Design Automation, pp. 373–377, Feb. 1993.

    Google Scholar 

  6. R. Ashenhurst, “The decomposition of switching functions,” in Int. Symp. of the Theory of Switching, 1957.

    Google Scholar 

  7. J. P. Roth and R. M. Karp, “Minimization of Boolean graphs,” IBM J. of Research and Development, Apr. 1962.

    Google Scholar 

  8. R. Rudell and A. Sangiovanni-Vincentelli, “Exact minimization of multiple-valued functions,” in Int. Conf. on CAD, pp. 352–355, Nov. 1986.

    Google Scholar 

  9. L. Pilaggi, “Achieving timing closure for giga-scale IC designs,” in ACM Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Mar. 1999.

    Google Scholar 

  10. A. Narayan, W. Gosti, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Wire planning in logic synthesis,” in Int. Conf. on CAD, pp. 26–33, Nov. 1998.

    Google Scholar 

  11. W. Gosti, Layout Aware Synthesis. PhD thesis, University of California, Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, Dec. 2000. Memorandum No. UCB/ERL MOO/67.

    Google Scholar 

  12. L. van Ginneken, “personal communication,” 2000. CAD seminar at UC Berkeley.

    Google Scholar 

  13. I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing East CMOS Circuits. San Francisco, CA: Morgan Kaufmann Publishers, Inc., 1999.

    Google Scholar 

  14. L. Pilaggi, “SIPs,” Dec. 2000. personal communication.

    Google Scholar 

  15. S. Borkar, “Circuit design challenges beyond 0.18 micron,” in Int. Symp. on Physical Design, Apr. 2000.

    Google Scholar 

  16. R. H. J. M. Otten and R. K. Brayton, “Planning for performance,” in DAC, pp. 122–127, June 1998.

    Google Scholar 

  17. D. Sylvester and K. Keutzer, “Getting to the bottom of deep submicron,” in Int. Conf. on CAD, pp. 203–211, Nov. 1998.

    Google Scholar 

  18. D. Sylvester and K. Keutzer, “Getting to the bottom of deep submicron II: A global wiring paradigm,” in Int. Symp. on Physical Design, pp. 193–200, Apr. 1999.

    Google Scholar 

  19. M. Bauer, R. Alexis, G. Atwood, R. Baltar, A. Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, and K. Wojciechowski, “A multilevel-cell 32Mb flash memory,” in 30th IEEE Int. Symp. on Multiple-Valued-Logic, May 2000.

    Google Scholar 

  20. S. Khatri, A. Mehrotra, R. K. Brayton, A. Sangiovanni-Vincentelli, and R. Otten, “A novel VLSI layout fabric for deep sub-micron applications,” in DAC, pp. 491–496, 1999.

    Google Scholar 

  21. S. Khatri, R. Brayton, and A. Sangiovanni-Vincentelli, “A VLSI design methodology using a network of PLAs embedded in a regular layout fabric,” Tech. Rep. UCB/ERL M99/50, Electronics Research Laboratory, University of California, Berkeley, May 1999.

    Google Scholar 

  22. J. Cong, H. Huang, and X. Yuan, “Technology mapping for k/m-macrocell based FPGAs,” in Int. Symp. on Field Programmable Gate Arrays, Feb. 2000.

    Google Scholar 

  23. N. Maheshwari and S. S. Sapatnekar, “Efficient retiming of large circuits,” IEEE Transactions on VLSI Systems, pp. 74–83, Mar. 1998.

    Google Scholar 

  24. J. Cong, S. K. Lim, and C. Wu, “Performance driven multi-level and multiway partitioning with retiming,” in DAC, pp. 274–279, June 2000.

    Chapter  Google Scholar 

  25. P. Chong and R. Brayton, “Characterization of feasible retimings,” in Int. Workshop on Logic Synthesis, pp. 1–6, June 2001.

    Google Scholar 

  26. J. L. da Silva jr., M. Sgroi, F. D. Bernardinis, S. Li, A. Sangiovanni-Vincentelli, and J. Rabaey, “Wireless protocols design: Challenges and opportunities,” in CODES, pp. 147–151, May 2000.

    Chapter  Google Scholar 

  27. J. Rowson and A. Sangiovanni-Vincentelli, “What you need to know about hardware/software co-design,” Computer Design, pp. 63–69, Aug. 1998.

    Google Scholar 

  28. G. Berry, “Esterel on hardware,” Phil. Trans, of Royal Society of London, pp. 87–104, 1992.

    Google Scholar 

  29. A. Domic, P. C. McGeer, A. Saldanha, and L. K. Scheffer, “CAD techniques for lower IC power consumption,” Computer Design, Apr. 1997.

    Google Scholar 

  30. R. I. Bahar, E. A. Frohm, C. M. Goana, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, “Algebraic decision diagrams and their applications,” in Int. Conf. on CAD, pp. 188–191, Oct. 1992.

    Google Scholar 

  31. Y. Jiang and R. Brayton, “Logic optimization and code generation in embedded control applications,” in CODES, pp. 225–229, Mar. 2001.

    Chapter  Google Scholar 

  32. A. Peymandoust and G. DeMicheli, “Using symbolic algebra in algorithmic level DSP synthesis,” in DAC, pp. 277–282, June 2001.

    Google Scholar 

  33. W. Kelly, V. Maslov, W. Pugh, E. Rosser, T. Shpeisman, and D. Wonnacott, “The Omega library (version 1.1.0) interface guide.” http://www.cs.umd.edu/projects/omega, Nov. 1996.

  34. T. R. Shiple, J. H. Kukula, and R. K. Ranjan, “A comparison of Presburger engines for EFSM reachability,” in CAV, pp. 280–292, June 1998.

    Google Scholar 

  35. J. G. Henriksen, J. Jensen, M. Jorgensen, N. Klarlund, R. Paige, T. Rauhe, and A. Sandholm, “Mona: Monadic second-order logic in practice,” in Tools and Algorithms for the Construction and Analysis of Systems, pp. 58–73, First Int. Workshop, TACAS, LNCS, Springer-Verlag, May 1995.

    Google Scholar 

  36. T. Amon, G. Borriello, and J. Liu, “Making complex timing relationships readable: Presburger formula simplification using don’t cares,” in DAC, pp. 586–590, June 1998.

    Google Scholar 

  37. Y. Watanabe and R. K. Brayton, “The maximum set of permissible behaviors for FSM networks,” in Int. Conf. on CAD, pp. 316–320, Nov. 1993.

    Google Scholar 

  38. A. Aziz, F. Balarin, R. Brayton, and A. Sangiovanni-Vincentelli, “Sequential synthesis using SIS,” in Int. Conf on CAD, pp. 612–617, Nov. 1995.

    Google Scholar 

  39. Y. Watanabe and R. K. Brayton, “State minimization of pseudo non-deterministic FSMs,” in European Conf. on Design Automation, pp. 184–191, Mar. 1994.

    Google Scholar 

  40. R. Brayton, A. Mehrotra, S. Qadeer, and V. Singhal, “Sequential optimization without state space exploration,” in Int. Workshop on Logic Synthesis, May 1997.

    Google Scholar 

  41. S. Malik, E. M. Sentovich, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Retiming and resynthesis: Optimization of sequential networks with combinational techniques,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 74–84, Jan. 1991.

    Article  Google Scholar 

  42. H. Cho, G. D. Hachtel, E. Macii, B. Plessier, and F. Somenzi, “Algorithms for approximate FSM traversal,” in DAC, pp. 25–30, June 1993.

    Google Scholar 

  43. S. Govindaraju, D. Dill, A. Hu, and M. Horowitz, “Approximate reachability analysis with BDDs using overlapping projections,” in DAC, pp. 451-455, June 1998.

    Google Scholar 

  44. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, “Engineering a (super?) efficient SAT solver,” in DAC, pp. 530–535, June 2001.

    Google Scholar 

  45. A. Gupta, Z. Yang, and P. Ashar, “SAT-based image computation with application in reachability analysis for verification,” in EMCAD, pp. 354–371, Nov. 2000.

    Google Scholar 

  46. A. Kuehlmann, M. Ganai, and V. Paruthi, “Circuit-based Boolean reasoning,” in DAC, pp. 232–237, June 2001.

    Google Scholar 

  47. E. Lawler, “An approach to multilevel Boolean minimization,” J. of the ACM, pp. 283\–295, July 1964.

    Google Scholar 

  48. M. Prasad, P. Chong, and K. Keutzer, “Why is ATPG easy?” in DAC, pp. 22–28, June 1999.

    Google Scholar 

  49. M. Prasad and E. Goldberg, “Improved SAT search,” Mar. 2001. personal communication.

    Google Scholar 

  50. B. Selman, H. Levesque, and D. Mitchell, “A new method for solving hard satisfiability problems” in Proc. AAAI-92, pp. 440–446, 1992.

    Google Scholar 

  51. B. Selman, H. Kautz, and B. Cohen, “Noise strategies for local search,” in Proc. AAAI-94, pp. 337–343, 1994.

    Google Scholar 

  52. S. Minato, “Zero-suppressed BDDs for set manipulation in combinatorial problems,” in DAC, pp. 272–277, June 1993.

    Google Scholar 

  53. A. Narayan, J. Jain, M. Fujita, and A. Sangiovanni-Vincentelli, “Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions,” in Int. Conf on CAD, pp. 547–554, Nov. 1996.

    Google Scholar 

  54. R. Bryant, D. Beatty, and C.-J. H. Seger, “Formal hardware verification by symbolic ternary trajectory evaluation,” in DAC, pp. 397–402, June 1991.

    Google Scholar 

  55. J. Yang and C.-J. H. Seger, “Generalized symbolic trajectory evaluation,” tech. rep., Intel Strategic CAD Labs, 2000.

    Google Scholar 

Download references

Authors
  1. Robert K. Brayton
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Tufts University, USA

    Soha Hassoun

  2. Kyushu Institute of Technology, Japan

    Tsutomu Sasao

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer Science+Business Media New York

About this chapter

Cite this chapter

Brayton, R.K. (2002). The Future of Logic Synthesis and Verification. In: Hassoun, S., Sasao, T. (eds) Logic Synthesis and Verification. The Springer International Series in Engineering and Computer Science, vol 654. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0817-5_15

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-0817-5_15

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5253-2

  • Online ISBN: 978-1-4615-0817-5

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation