Abstract
This article describes a method used commercially for checking the correctness of integrated circuit designs. The method is applicable to the development of “control-intensive” software programs as well. “Divide-and-conquer” techniques central to this method apply to a broad range of program verification methodologies.
A shorter version of this article appeared with the title “Program Verification” in the May 2000 issue of the Notices of the American Mathematical Society, 47 (5), pp. 534–545, and this article appears with their permission.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Barwise. Mathematical Proofs of Computer System Correctness. Notices 36, pages 844–851, 1989.
W. W. Bledsoe and D. W. Loveland, editors. Automated Theorem Proving: After 25 Years, Contemporary Math 29. Amer. Math. Soc., 1984. Especially Proof-Checking, Theorem-Proving and Program Verification by R. S. Boyer and J. S. Moore, 119–132.
F. P. Brooks, Jr. The Mythical Man Month. Addison-Wesley, anniversary edition, 1995.
R. E. Bryant. Graph Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers C-35, pages 677–691, 1986.
A. W. Burks, H. H. Goldstine, and J. von Neumann. Preliminary Discussion of the Logical Design of an Electronic Computing Instrument. U.S. Army Ordnance Department, 1946.
K. M. Chandy and J. Misra. Parallel Program Design: A Foundation. Addison-Wesley, Reading, Mass., 1988.
E. M. Clarke and E. A. Emerson. Design and Synthesis of Synchronization Skeletons Using Branching Time Temporal Logic. In Logic of Programs: Workshop, Yorktown Heights, NY, May 1981, Lecture Notes in Computer Science 131. Springer-Verlag, 1981.
E. M. Clarke, Jr., O. Grumberg, and D. Peled. Model Checking. MIT Press, 1999.
R. DeMillo, R. Lipton, and A. Perlis. Social Processes and Proofs of Theorems and Programs. Communications of the ACM 22 (5), pages 271–280, 1979.
E. W. Dijkstra. Hierarchical Ordering of Sequential Processes. Acta Informatica, Springer Verlag, 1(2): 115–138, October 1971.
E. W. Dijkstra, editor. Formal Development of Programs and Proofs. University of Texas at Austin Year of Programming series. Addison-Wesley, 1990.
M. A. Dornheim. Faulty Thruster Table Led to Mars Mishap. Aviation Week and Space Technology, pages 40–41, October 1999.
[13] E. A. Emerson. Temporal and Modal Logic. In Handbook of Theoretical Computer Science, volume B, chapter 16, pages 995–1072. Elsevier, 1990.
[14] E. A. Emerson and C. L. Lei. Efficient Model Checking in Fragments of the Propositional Mu-Calculus. In Proc. Symposium Logic in Computer Science (LICS), pages 267–278. IEEE, 1986.
P. Halmos. Lectures on Boolean Algebras. Springer-Verlag, 1974.
Z. Har’El and R. P. Kurshan. Software for the Analytical Development of Communications Protocols. AT&T Tech. J. 69, pages 45–59, 1990.
O. Kupferman, R. P. Kurshan, and M. Yannakakis. Existence of Reduction Hierarchies. Lecture Notes in Computer Science, 1414:327–340, 1998.
R. P. Kurshan. Computer-aided Verification of Coordinating Processes — The Automata-Theoretic Approach. Princeton Univ. Press, 1994.
N. G. Leveson and C. S. Turner. An Investigation of the Therac-25 Accidents. Computer, 26(7):18–41, July 1993.
Z. Manna and A. Pnueli. The Temporal Logic of Reactive and Concurrent Systems. Springer, New York, 1992.
C. Mason and D. Bushaus. Software problem cripples AT&T longdistance network. Telephony, 218(4): 10–11, January 1990.
S. McConnell. Code Complete. Microsoft Press, 1993.
K. L. McMillan. Symbolic Model Checking. Kluwer, 1993.
K. L. McMillan. Verification of Infinite State Systems by Compositional Model Checking. In L. Pierre and T. Kropf, editors, Correct Hardware Design and Verification Methods, CHARME′99, Lecture Notes in Computer Science 1703, pages 219–233. Springer, 1999.
I. Peterson. Software Failure: Counting up the Risks. Science News 140, page 388, 1991.
J. P. Queille and J. Sifakis. Specification and Verification of Concurrent Systems in CESAR. Lecture Notes in Computer Science 137, pages 337-351, 1982.
S. Schroeder. Turning to Formal Verification. Integrated System Design Magazine, pages 1–5, September 1997.
P. Sparaco. Board Faults Ariane 5 Software. Aviation Week and Space Technology, pages 33–34, July 1996.
M. Y. Vardi and P. Wolper. An Automata-Theoretic Approach to Automatic Program Verification. In Proc. (1st) IEEE Symposium on Logic in Computer Science, pages 322–331, Boston, 1986.
N. Wirth. Program Development by Stepwise Refinement. Communications of the ACM, 14(4):221–227, 1971.
A. Wolfe. Intel Fixes a Pentium FPU Glitch. EETimes, 882, November 1994.
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer Science+Business Media New York
About this chapter
Cite this chapter
Kurshan, R.P. (2001). Formal Verification of Circuit Designs. In: Datta, B.N. (eds) Applied and Computational Control, Signals, and Circuits. The Springer International Series in Engineering and Computer Science, vol 629. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1471-8_4
Download citation
DOI: https://doi.org/10.1007/978-1-4615-1471-8_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5570-0
Online ISBN: 978-1-4615-1471-8
eBook Packages: Springer Book Archive