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SOI Devices

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Electrical Characterization of Silicon-on-Insulator Materials and Devices

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 305))

Abstract

Silicon-on-insulator devices and circuits have progressed at a remarkable rate during the past several years. The theoretical advantages of SOI over bulk silicon, summarized in Chapter 1, have been fully demonstrated in terms of performance and reliability. Recent interest has turned to possible use of fully depleted SOI films for deep submicron circuits. Other areas in which the capability of SOI has been identified include low-power and mixed-technology circuits. In this chapter, we shall review a number of typical SOI devices, circuits, and related applications. Among them are the radiation-hardened CMOS circuits, the advanced CMOS ULSI, high/low voltage, high temperature devices, three-dimensional circuits, and sensors. Some innovative and speculative components will be presented in the last section.

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Bibliography

  1. T. Tsuchiya, T. Ohno, and Y. Kado, “Present status and potential of subquarter-micron ultra-thin-film CMOS/SIMOX technology,” in SiliconOn-Insulator Technology and Devices, S. Cristoloveanu (ed.), The Electrochemical Society, Pennington, NJ, p. 401, 1994.

    Google Scholar 

  2. J. Chen, S. Parke, J. King, F. Assaderaghi, P. Ko, and C. Hu, “A highspeed SOI technology with 12 ps/18 ps gate delay operating at 5V/1.5 V,” IEDM’92 Tech. Digest, p. 35, 1992.

    Google Scholar 

  3. K. Aubuchon, J. Pinter, M. Matloubian, M. Barger, R. McClain, and O. Marsh, “Initial evaluation of CMOS/SOI fabricated on plasma-thinned bonded silicon wafers,” Int. SOI Conf. Proc., p. 154, 1992.

    Google Scholar 

  4. Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, “0.1 µm gate, ultrathinfilm CMOS devices using SIMOX substrate with 80 nm thick buried oxide layer,” IEEE Trans. Electron Devices, vol. 40, p. 1019, 1993.

    Article  Google Scholar 

  5. K. Suzuki, T. Tanaka, Y. Tosaka, T. Sugii, and S. Andoh, “Source/drain contact resistance of silicided thin-film SOI MOSFETs,” IEEE Trans. Electron Devices,vol. 41, p. 1007, 1994.

    Article  Google Scholar 

  6. Y. Yamaguchi, T. Nishimura, Y. Akasaka, and K. Fujibayashi, “Self-aligned silicide technology for ultra-thin SIMOX MOSFETs,” IEEE Trans. Electron Devices, vol. 39, p. 1179, 1992.

    Article  Google Scholar 

  7. L.T. Su, M.J. Sherony, J.E. Chung, and D.A. Antoniadis, “Optimization of series resistance in sub-0.2 pm SOI MOSFETs,” IEEE Electron Device Lett., vol. 15, p. 145, 1994.

    Article  Google Scholar 

  8. O. Faynot and B. Giffard, “High performance ultrathin SOI MOSFETs obtained by localized oxidation,” IEEE Electron Device Lett., vol. 15, p. 175, 1994.

    Article  Google Scholar 

  9. M. Chan, F. Assaderaghi, S.A. Parke, C. Hu, and P.K. Ko, “Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance,” IEEE Electron Device Lett., vol. 15, p. 22, 1994.

    Article  Google Scholar 

  10. L.T. Su, J.B. Jacobs, J.E. Chung, and D.A. Antoniadis, “Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFETs,” IEEE Electron Device Lett., vol. 15, p. 183, 1994.

    Article  Google Scholar 

  11. M. Rodder, “Silicon-on-insulator bipolar transistor,” IEEE Electron Device Lett., vol. 4, p. 193, 1983.

    Article  Google Scholar 

  12. B.Y. Tsaur, “Fully-isolated lateral bipolar-MOS transistors fabricated in zone melting recrystallized Si films on Si02,” IEEE Electron Device Lett., vol. 4, p. 269, 1983.

    Article  Google Scholar 

  13. J.P. Colinge, “Half-micrometer base lateral bipolar transistors made in thin silicon-on-insulator films,” Electron. Lett., vol. 22, p. 886, 1986.

    Article  Google Scholar 

  14. J-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer, Boston, 1991.

    Book  Google Scholar 

  15. N. Higaki, T. Fukano, and A. Fukuroda, “A thin-base lateral bipolar transistor fabricated on bonded SOI,” Symp. VLSI Tech. Proc., p. 53, 1991.

    Google Scholar 

  16. G.G. Shahidi, D.D. Tang, and B. Davari, “A novel high-performance lateral bipolar transistor formed on SOI substrate,” IEDM’91 Tech. Digest, p. 633, 1991.

    Google Scholar 

  17. S.A. Parke, C. Hu, and P.K. Ko, “Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs,” IEEE Electron Device Lett., vol. 14, p. 234, 1993.

    Article  Google Scholar 

  18. M.D. Church, “A comparative study of functional 16K bipolar PROM circuits fabricated on bonded, oxide isolated and junction isolated substrates,” IEEE Int. SOI Conf. Proc., p. 175, 1989.

    Google Scholar 

  19. H.J. Shin, C.L. Chen, E.D. Johnson, Y. Taur, S. Ramaswamy, and G. Bourdon, “Full-swing complementary BiCMOS logic circuits,” IEEE BCTM Conf. Proc., p. 229, 1989.

    Google Scholar 

  20. G.G. Shahidi, “SOI: opportunities and challenges for sub-0.25 µm VLSI,” IEEE BCTM Conf. Proc., p. 255, 1992.

    Google Scholar 

  21. T. Hiramoto, N. Tamba, M. Yoshida, T. Hashimoto, T. Fujiwara, K. Watanabe, M. Odaka, M. Usami, and T. Ikeda, “A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58µm2 CMOS memory cells for ECL-CMOS SRAM applications,” IEDM’92 Tech. Digest, p. 39, 1992.

    Google Scholar 

  22. J.L. Leray, E. Dupont-Nivet, J.F. Peret, Y.M. Coïc, M. Raffaelli, A.J. Auberton-Hervé, M. Bruel, B. Giffard, and J. Margail, “CMOS/SOI hardening at 100 Mrad (Si02),” IEEE Trans. Nucl. Sci., vol. 37, p. 2013, 1990.

    Article  Google Scholar 

  23. H. Lu, E. Yee, L. Hite, T. Houston, Y. Sheu, R. Rajgopal, C.C. Shen, J.M. Hwang, and G. Pollack, IEEE Int. Solid State Circuits Conf. Digest, p. 182, 1993.

    Google Scholar 

  24. L.R. Hite, H. Lu, T.W. Houston, D.S. Hurta, and W.E. Bailey, “An SEU resistant 256 1(SOI SRAM,” IEEE Trans. Nucl. Sci., vol. 39, p. 2121, 1992.

    Article  Google Scholar 

  25. J.P. Colinge, M.H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator gate-all-around device,” IEDM’90 Tech. Digest, p. 595, 1990.

    Google Scholar 

  26. E. Simoen, U. Magnusson, I. Born, J. Vlummens and C. Claeys, “Mrad(Si) irradiation effects in GAA SOI nMOSFETs,” in Silicon-On-Insulator Technology and Devices, S. Cristoloveanu (ed.), The Electrochemical Society, Pennington, NJ, p. 375, 1994.

    Google Scholar 

  27. E. Arnold, S. Merchant, M. Amato, S. Mukherjee, H. Pein, and A. Ludikhuize, “Comparison of junction isolated and SOI high voltage devices in source follower mode,” 4th Int. Symp. Power Semiconductor Dev. Proc., p. 242, 1992.

    Google Scholar 

  28. E. Arnold, “Silicon-on-insulator devices for high voltage and power IC applications,” J. Electrochem. Soc., vol. 141, p. 1983, 1994.

    Article  Google Scholar 

  29. B. Edholm, J. Olsson, and A. Söderbärg, “A self-aligned lateral bipolar transistor realized on SIMOX material,” IEEE Trans. Electron Devices, vol. 40, p. 2359, 1993.

    Article  Google Scholar 

  30. I.J. Kim, S. Matsumoto, T. Sakai, and T. Yachi, “Breakdown voltage improvement for thin-film SOI power MOSFETs by a buried oxide step structure,” IEEE Electron Device Lett., vol. 15, p. 148, 1994.

    Article  Google Scholar 

  31. T. Ohno, S. Matsumoto, and K. Izumi, “An intelligent power IC with double buried-oxide layers formed by SIMOX technology,” IEEE Trans. Electron Devices, vol. 40, p. 2074, 1993.

    Article  Google Scholar 

  32. H. Vogt, “Advantages and potential of SOI structures for smart sensors,” in Silicon-On-Insulator Technology and Devices, S. Cristoloveanu (ed.), The Electrochemical Society, Pennington, NJ, p. 430, 1994.

    Google Scholar 

  33. J.D. Beasom, “120 V AC, 250 V DC monolithic power supply made with bonded wafer technology,” Int. SOI Conf. Proc., p. 66, 1992.

    Google Scholar 

  34. J.M. O’Connor, V.K. Luciani, and A.L. Caviglia, “High voltage DMOS power FETs on thin SOI substrates,” Int. SOI Conf. Proc., p. 167, 1990.

    Google Scholar 

  35. H. Pein, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S. Merchant, and S. Mukherjee, “SOI high voltage LDMOS and LIGBT transistors with a buried diode and surface p-layer,” Int. SOI Conf. Proc., p. 146, 1992.

    Google Scholar 

  36. T. Ouisse, G. Reichert, S. Cristoloveanu, O. Faynot, and B. Giffard, “Analysis of SIMOX MOS transistors operated in the high temperature range,” Mat. Sci. Eng. B, 1995.

    Google Scholar 

  37. P. Francis, A. Terao, B. Gentinne, D. Flandre, and J.P. Colinge, “SOI technology for high-temperature applications,” IEDM’92 Tech. Digest, p. 353, 1992.

    Google Scholar 

  38. D. Flandre, C. Jacquemin, and J.P. Colinge, “Design techniques for highspeed and low-power and high-temperature digital CMOS circuits on SOI,” Int. SOI Conf. Proc.,p. 164, 1992.

    Google Scholar 

  39. T.W. Houston, H. Lu, P. Mei, T.G.W. Blake, L.R. Hite, T. Sundaresan, M. Matloubian, W.E. Bailey, J. Liu, A. Peterson, and G. Pollack, “A 1 µm CMOS/SOI 64K SRAM with 10nA standby current,” IEEE SOS/SOI Technol. Conf. Proc., p. 137, 1989.

    Google Scholar 

  40. S.R. Wilson, B.Y. Hwang, J. Foerstner, T. Wetteroth, M. Racanelli, J. Tsao, and M. Huang, “Requirements for TFSOI materials and their effects on devices,” in Silicon-On-Insulator Technology and Devices, S. Cristoloveanu (ed.), The Electrochemical Society, Pennington, NJ, p. 413, 1994.

    Google Scholar 

  41. H. Achard, J.L. Mermet, H. Bono, J.P. Joly, and A. Monroy, “Contribution to the use of laser recrystallization on top of existing devices,” Eur. SOI Conf. Proc., p. B-03, 1988.

    Google Scholar 

  42. R.P. Zingg, J. Friedrich, G.W. Neudeck, and B. Hoefflinger, “Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth,” IEEE Trans. Electron Devices, vol. 37, p. 1452, 1990.

    Article  Google Scholar 

  43. G.W. Neudeck, “Three-dimensional CMOS integration,” IEEE Circuits Devices, vol. 6, p. 32, 1990.

    Article  Google Scholar 

  44. S. Hirose, T. Nishimura, K. Sugahara, S. Kusunoki, Y. Akasaka, and N. Tsubouchi, “A 10-bit linear image sensor fabricated in double active layers,” 1985 Symp. VLSI Tech. Conf. Proc., p. 34, 1985.

    Google Scholar 

  45. T. Nishimura, Y. Inoue, K. Sugahara, M. Nakaya, Y. Horiba, and Y. Akasaka, “A three dimensional static RAM,” 1985 Symp. VLSI Tech. Conf. Proc., p. 30, 1985.

    Google Scholar 

  46. K. Sugahara, T. Nishimura, S. Kusonoki, Y. Akasaka, and H. Nakata, “SOI/SOI/bulk-Si triple-level structure for three-dimensional devices,” IEEE Electron Device Lett., vol. 7, p. 193, 1986.

    Article  Google Scholar 

  47. T. Nishimura, Y. Inoue, K. Sugahara, S. Kusonoki, T. Kumamoto, S. Nakagawa, M. Nakaya, Y. Horiba, and Y. Akasaka, “Three dimensional IC for high performance image signal processor,” IEDM’87 Conf. Proc., p. 111, 1987.

    Google Scholar 

  48. R. Watts, A.L. Robinson, and R.A. Soref, “Electromechanical optical switching and modulation in micromachined silicon-on-insulator wave-guides,” Int. SOI Conf. Proc., p. 62, 1991.

    Google Scholar 

  49. S. Cristoloveanu, “Advanced silicon on insulator materials: processing, characterization and devices,” in Semiconductor Silicon, G. Harbeke and M.J. Schulz (eds.), Springer, Berlin, p. 223, 1989.

    Chapter  Google Scholar 

  50. S. Cristoloveanu, “Integrated magnetic sensors: an overview,” J. Korean Inst. Electron. Eng., p. 86, 1986.

    Google Scholar 

  51. P. Lilienkamp and H. Pfleiderer, “An EFSI-SOS magnetodiode,” Phys. Status Solidi (a), vol. 43, p. 479, 1977.

    Article  Google Scholar 

  52. S. Cristoloveanu, “Magnetic field and surface influences on double injection phenomena in semiconductors: the magnetodiode effect theory,” Phys. Status Solidi (a), vol. 64, p. 683 and vol. 65, p. 281, 1981.

    Google Scholar 

  53. A. Mohaghegh, S. Cristoloveanu, and J. de Pontcharra, “Double injection phenomena under magnetic field in SOS films. A new generation of magnetosensitive micro-devices,” IEEE Trans. Electron Devices, vol. 28, p. 237, 1981.

    Article  Google Scholar 

  54. W.B. Dubbelday, L.D. Flesner, G.A. Garcia, G.P. Imthurm, and R.J. Hirschi, “Very high voltage photocell arrays,” Int. SOI Conf. Proc., p. 84, 1991.

    Google Scholar 

  55. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon on insulator transistor with volume inversion: a new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. 8, p. 410, 1987.

    Article  Google Scholar 

  56. D. Hisamoto, T. Kaga, and E. Takeda, “Impact of the vertical SOI `DELTA’ structure on planar device technology,” IEEE Trans. Electron Devices, vol. 38, p. 1419, 1991.

    Google Scholar 

  57. J.P. Colinge, X. Baie, and V. Bayot, “Evidence of two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices,” IEEE Electron Device Lett., vol. 15, p. 193, 1994.

    Article  Google Scholar 

  58. Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, “Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs,” IEEE Electron Device Lett., vol. 14, p. 569, 1993.

    Article  Google Scholar 

  59. T. Ouisse, S. Cristoloveanu, and D.K. Maude, “Experimental investigation of silicon-on-insulator metal-oxide-semiconductor field-effect transistors at high magnetic field and low temperature,” J. Appl. Phys., vol. 74, p. 408, 1993.

    Article  Google Scholar 

  60. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, “Modeling of ultra-thin double-gate nMOS/SOI transistors,” IEEE Trans. Electron Devices, vol. 41, p. 715, 1994.

    Article  Google Scholar 

  61. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 40, p. 2326, 1993.

    Article  Google Scholar 

  62. E. Simoen, U. Magnusson, and C. Claeys, “A low-frequency noise study of gate-all-around SOI transistors,” IEEE Trans. Electron Devices, vol. 40, p. 2054, 1993.

    Google Scholar 

  63. M.H. Gao, J-P. Colinge, L. Lauwers, S-H. Wu, and C. Claeys, “TwinMOSFET structure for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures,” Solid-State Electron., vol. 35, p. 505, 1992.

    Article  Google Scholar 

  64. M.H. Gao, S.H. Wu, J-P. Colinge, C. Claeys, and G. Declerck, “Single device inverter using SOI cross-MOSFETs,” Int. SOI Conf. Proc., p. 138, 1991.

    Google Scholar 

  65. J.F. Gibbons and G. Declerck, “Single device inverter using SOI crossMOSFETs,” IEEE Electron Device Lett., vol. 3, p. 191, 1982.

    Article  Google Scholar 

  66. T.I. Kamins, P.J. Marcoux, J.L. Moll, and L.M. Roylance, “Patterned implanted buried-oxide transistor structures,” J. Appl. Phys., vol. 60, p. 423, 1986.

    Article  Google Scholar 

  67. A.K. Agarwal, M.H. Hanes, T.W. O’Keeffe, J.R. Szedon, H.M. Hobgood, T.J. Smith, R.R. Siergiej, C.D. Brandt, M.C. Driver, R.N. Thomas, and H.C. Nathanson, “MICROX™: an all silicon microwave technology,“ Int. SOI Conf. Proc., p. 144, 1992.

    Google Scholar 

  68. J. Schmidtchen, A. Splett, B. Schüppert, and K. Petermann, “Low loss integrated-optical rib-waveguides in SOI,” Int. SOI Conf. Proc., p. 142, 1991.

    Google Scholar 

  69. X. Xiao, J.C. Sturm, P.V. Schwartz, and K.K. Goel, “Vertical 1.3 pm optical modulator in silicon-on-insulator,” Int. SOI Conf. Proc., p. 171, 1990.

    Google Scholar 

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Authors and Affiliations

  1. Polytechnic Institute of Grenoble, France

    Sorin Cristoloveanu

  2. University of Florida, USA

    Sheng S. Li

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  1. Sorin Cristoloveanu
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Cristoloveanu, S., Li, S.S. (1995). SOI Devices. In: Electrical Characterization of Silicon-on-Insulator Materials and Devices. The Springer International Series in Engineering and Computer Science, vol 305. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2245-4_3

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  • DOI: https://doi.org/10.1007/978-1-4615-2245-4_3

  • Publisher Name: Springer, Boston, MA

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