Abstract
Since the dominant component of power consumption for a properly designed CMOS circuit is proportional to the square of the supply voltage, operating circuits at the lowest voltage is the key to minimizing the energy consumed per operation. However, the individual circuit elements run slower at lower supply voltages (Figure 3.25) and this must be compensated for through appropriate architectural design. One important class of applications are those which have no advantage in exceeding a bounded computation rate, as found in real-time signal processing. The strategies presented in this chapter also have some applicability to the maximum throughput situation of general purpose computing though additional system level trade-offs must be made.
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© 1995 Springer Science+Business Media New York
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Chandrakasan, A.P., Brodersen, R.W. (1995). Voltage Scaling Approaches. In: Low Power Digital CMOS Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2325-3_4
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DOI: https://doi.org/10.1007/978-1-4615-2325-3_4
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