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The Superblock: An Effective Technique for VLIW and Superscalar Compilation

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Instruction-Level Parallelism

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 235))

Abstract

A compiler for VLIW and superscalar processors must expose sufficient instruction-level parallelism (ILP) to effectively utilize the parallel hardware. However, ILP within basic blocks is extremely limited for control-intensive programs. We have developed a set of techniques for exploiting ILP across basic block boundaries. These techniques are based on a novel structure called the superblock. The superblock enables the optimizer and scheduler to extract more ILP along the important execution paths by systematically removing constraints due to the unimportant paths. Superblock optimization and scheduling have been implemented in the IMPACT-I compiler. This implementation gives us a unique opportunity to fully understand the issues involved in incorporating these techniques into a real compiler. Superblock optimizations and scheduling are shown to be useful while taking into account a variety of architectural features.

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Authors and Affiliations

  1. Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL, 61801, USA

    Wen-Mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, John G. Holm & Daniel M. Lavery

Authors
  1. Wen-Mei W. Hwu
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  2. Scott A. Mahlke
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  3. William Y. Chen
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  4. Pohua P. Chang
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  5. Nancy J. Warter
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  6. Roger A. Bringmann
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  7. Roland G. Ouellette
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  8. Richard E. Hank
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  9. Tokuzo Kiyohara
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  10. Grant E. Haab
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  11. John G. Holm
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  12. Daniel M. Lavery
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Editor information

Editors and Affiliations

  1. Hewlett-Packard Laboratories, UK

    B. R. Rau  & J. A. Fisher  & 

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© 1993 Springer Science+Business Media New York

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Hwu, WM.W. et al. (1993). The Superblock: An Effective Technique for VLIW and Superscalar Compilation. In: Rau, B.R., Fisher, J.A. (eds) Instruction-Level Parallelism. The Springer International Series in Engineering and Computer Science, vol 235. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3200-2_7

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  • DOI: https://doi.org/10.1007/978-1-4615-3200-2_7

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  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6404-7

  • Online ISBN: 978-1-4615-3200-2

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