Global Routing Architecture

Abstarct

In this chapter we investigate which global routing architectures lead to the best FPGA area-efficiency [2, 3]. We use the term global routing architecture to refer to the distribution of routing tracks across an FPGA; that is, the relative number of tracks contained in each channel of the FPGA. In the next section we describe some of the different types of global routing architectures, and explain why this is an important problem in FPGA design. Section 5.2 describes the experimental flow we use to evaluate different global routing architectures — this flow is based on the CAD tools described in Chapters 3 and 4. In Section 5.3 we investigate directionally-biased global routing architectures, in which the channels in the vertical direction have a different width than those in the horizontal direction. Section 5.4 examines non-uniform global routing architectures, which have wider channels in some regions of the FPGA than in others.