Abstract
GaAs digital circuits have been much heralded as a means for achieving high computational throughput rates. For example, recently Hughes has published accounts of a flip-flop exhibiting toggle rates approaching 20 GHz using 0.2 micron BFL-CEL MESFET logic operating at room temperature. This impressive performance must, however, be taken in the context of the severe yield problems which inhibit the use of this technology in a cost effective manner in large systems. This leads to the fabrication of big systems using a large number of relatively small dies. Use of conventional packaging for such small dies then introduces parasitics which largely negate the performance improvements promised by the underlying GaAs technology. In this paper we examine one approach to packaging a large number of small GaAs circuits to implement a system of 1000 heavily pipelined systolic processors each operating at a rate of 1 billion floating point operations a second resulting in a sustained throughput of 1000 GFLOPS. This stunning performance could be accomplished using a package with a volume of a few cubic feet, and dissipating only about 10 KW of power. The impact on aerospace tactical and strategic signal processing applications of such a technology could be substantial.
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© 1988 Plenum Press, New York
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Merchant, H., Greub, H., Philhower, R., Majid, N., McDonald, J.F. (1988). Piggyback WSI GaAs Systolic Engine. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_4
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DOI: https://doi.org/10.1007/978-1-4684-5511-3_4
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