Abstract
As 1149.1 is so new, the topic of advanced 1149.1 testing is also quite new. Some of the techniques that have been proposed are speculative and have yet to be widely implemented and thoroughly proven. Yet, the promise for new testing capabilities is strong and exciting, just in time for some really formidable testing challenges on the horizon.
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Warning! If an IC input pin is attached directly to a Boundary Register cell without an intervening input buffer, then input parametric tests might prove that the Boundary Register works within DC parametric limits, but might not prove the same for the System Logic. This statement is true regardless of whether the cell design is a full implementation or an Observe-Only design.
The paper offers a probabilistic argument for how this technique will improve fault coverage. Intuitively, one can see how having hundreds of extra observation points available by means of concurrent sampling can help detect faults that might have been excited, but not propagated to a conventional observation point, which in the case of test microcode, is the test-and-branch unit of the test controller.
Note that the IBM work [Wagn91] was not done with an 1149.1 compliant design although there is no reason why it could not be as the authors point out. Locating the MISAR that monitors several TDO pins in an 1149.1-compliant component might be stretching the rules of the Standard. This is a system-test issue that might yet require resolution.
Packaging techniques such as Surface Mount Technology (SMT) are rapidly making sockets obsolete.
This cannot hope to approach the accuracy that a tester with full nodal access can enjoy, since some of our resources are controlled by Boundary-Scan resources through intervening TAPs in several dispersed ICs. We do not have control of the skews and errors that these will introduce.
A homing sequence requires the tester to apply input patterns, examine component outputs, and make decisions as to what patterns to apply next based on the observed outputs. If the outputs that must be observed are only visible by means of the scan process, this greatly complicates the decision logic.
From the point of view of the 1149.1 Working Group, differential drivers and receivers should be viewed as instances of the analog/digital configuration shown in Figure 4–7.
Other components may also be placed, such as surface mounted capacitors. Integral thin-film resistors may be part of the substrate as well.
MCMs are expensive today, but offer decreased size/weight, higher reliability, and higher operating frequencies (when properly utilized). The workstation (performance) and the laptop/palmtop computer (size/weight) marketplaces are two areas where MCMs hold good interest.
The netlist information need not be completely specified for board testing application if you assume that once successfully fabricated, the internal MCM interconnect will not break. It is sufficient to document only those nodal connections that reach an MCM I/O pin. Leaving internal interconnects undocumented may eace concern for those who want to keep this information secret.
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© 1992 Springer Science+Business Media New York
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Parker, K.P. (1992). Advanced Boundary-Scan Testing. In: The Boundary-Scan Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2142-3_4
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DOI: https://doi.org/10.1007/978-1-4757-2142-3_4
Publisher Name: Springer, Boston, MA
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