Abstract
Testing the adherence of a hardware description language (HDL) tool to an associated HDL specification is of critical importance to design teams. This paper will develop practical test suite requirements, outline FTL System’s VIVATM technology for automatically generating and applying test suites, and describe the experimental results using VIVA (VHDL Interactive Validation Alchemy) to test FTL Systems’ Auriga ® family of HDL compilers.
was with FTL Systems as a student intern and with the University of Cincinnati. He is currently at Intel.
was with FTL Systems as a student intern and is currently with the University of Cincinnati.
is the President and CEO of FTL Systems.
was with FTL Systems and is currently at The University of Tennessee.
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References
John Willis, Philip A. Wilsey, Gregory D. Peterson, John Hines, and William Dashiell, “Semi-Automatic Validation of VHDL & Related Languages.” In the Proceedings of the Fall 1996 VHDL International Users’ Forum.
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Sathyanarayanan Seshadri, An Approach to Automatic Test Generation for Evaluating VHDL AMS Simulators, Master of Science Thesis, University of Cincinnati, July, 2000.
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© 2001 Springer Science+Business Media New York
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Seshadri, S., Thiyagarajan, S., Willis, J., Peterson, G.D. (2001). Automating the Validation of Hardware Description Language Processing Tools. In: Ashenden, P.J., Mermet, J.P., Seepold, R. (eds) System-on-Chip Methodologies & Design Languages. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3281-8_20
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DOI: https://doi.org/10.1007/978-1-4757-3281-8_20
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-4901-1
Online ISBN: 978-1-4757-3281-8
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