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Peripheral Cell Design for IEEE 1149.4

Guide for the Integrated Circuit Designer

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Analog and Mixed-Signal Boundary-Scan

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 16))

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Abstract

IEEE 1149.4 can help improve system testability, time to market, and even performance through the miniaturization of interconnects and improved characterization. The main cost for a mixed signal design is the addition of some switches and their associated parasitics. This chapter describes how an integrated circuit designer can add those switches, or the functional equivalent, without compromising performance.

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References

  1. J. E. McDermid, S. Oresjo, “Structure and Metrology for an Analog Testability Bus”, K. P. Parker, Proceedings, International Test Conference, pp. 309–322, Baltimore, MD, October 1993

    Google Scholar 

  2. K Lofstrom, “A Demonstration IC for the P1149.4 Mixed-Signal Test Standard”, Proceedings, International Test Conference, pp. 417–422, Washington, DC, October 1996

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  3. K P. Parker, J. E. McDermid, R. A. Browen, K Nuria. K Hirayama, A. Matsuzawa, “Design, Fabrication, and Use of Mixed-Signal IC Testability Structures”, Proceedings, International Test Conference, pp. 489–498, Washington, DC, November 1997

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  4. IEEE, “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standard 1149.1–1990. IEEE Standards Board, 345 East 47th St. New York, NY 10017, 1990

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  5. IEEE, “IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interfaces (SCI)”IEEE Standard 1596.3–1996. IEEE Standards Board, 345 East 47th St. New York, NY 10017, 1996

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  6. IEEE, “IEEE Standard for a Mixed Signal Test Bus”, IEEE Standard 1149.4–1999. IEEE Standards Board, 345 East 47th St. New York, NY 10017, 1999

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  7. IEEE, “Draft Standard for Boundary-Scan-Based In-System Configuration of Programmable Devices”, IEEE Standard 15322000. IEEE Standards Board, 345 East 47th St. New York, NY 10017, 2000

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© 1999 Springer Science+Business Media Dordrecht

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Lofstrom, K. (1999). Peripheral Cell Design for IEEE 1149.4. In: Osseiran, A. (eds) Analog and Mixed-Signal Boundary-Scan. Frontiers in Electronic Testing, vol 16. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4499-6_5

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  • DOI: https://doi.org/10.1007/978-1-4757-4499-6_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5115-1

  • Online ISBN: 978-1-4757-4499-6

  • eBook Packages: Springer Book Archive

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