Introduction

Abstract

In volume I of this two-volume set we examined the architectural techniques that have been used to produce high performance computers. This included techniques to maximise processor performance; for example, instruction pipelines and parallel functional units. It also included techniques to maximise the throughput, and minimise the latency, of storage structures; for example, interleaving and caching respectively. We saw how these design techniques can be brought together in the form of vector processors in order to provide a platform for very high performance numerical processing. However, all the machines considered in volume I have something in common; they operate within a relatively conventional programming model, and this means that high-level language programs written for one high performance architecture will work equally well on another, with little or no modification. In this book we are concerned with architectures for which this does not necessarily hold true, and for which new languages and new application algorithms are required. This naturally implies a greater overall design effort, but in many cases this is outweighed by the resulting gain in performance.