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A Framework for Non-intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration

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Runtime Verification (RV 2018)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 11237))

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Abstract

Traditional software testing methods are inefficient for multithreaded software. In order to verify such software, testing is often complemented by analysis of the execution trace. To monitor the execution trace, most approaches today use binary instrumentation or rigid frameworks based on system simulators. Most existing approaches are intrusive, as they tend to change the monitored software. Furthermore, their monitoring configuration is static, resulting in huge, often non-relevant, traces. In this paper, we present a light, non-intrusive execution monitoring and control approach, implemented using the gem5 system simulator. We complement existing approaches with dynamic configuration of the monitoring, making it possible to dynamically change the monitoring focus to the parts of the software that are of interest. This configuration results in reduced execution trace size. Our approach does not change the software under test, but rather the virtual platform that executes the software.

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References

  1. Adrien, V., Naser, E.J., Dagenais, M.R.: Hardware-assisted software event tracing. Concurr. Comput.: Pract. Exp. 29(10), e4069 (2017). https://doi.org/10.1002/cpe.4069. https://onlinelibrary.wiley.com/doi/abs/10.1002/cpe.4069

    Article  Google Scholar 

  2. Agarwal, R., Sasturkar, A., Wang, L., Stoller, S.D.: Optimized run-time race detection and atomicity checking using partial discovered types. In: Proceedings of the 20th IEEE/ACM International Conference on Automated Software Engineering, ASE 2005, pp. 233–242. ACM, New York (2005). https://doi.org/10.1145/1101908.1101944, http://doi.acm.org/10.1145/1101908.1101944

  3. Alpern, B., et al.: The jalapeno virtual machine. IBM Syst. J. 39(1), 211–238 (2000). https://doi.org/10.1147/sj.391.0211

    Article  Google Scholar 

  4. Apache-commons: the byte code engineering library (apache commons bcel) (2017). http://jakarta.apache.org/bcel/

  5. Binkert, N., et al.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011). https://doi.org/10.1145/2024716.2024718, https://doi.acm.org/10.1145/2024716.2024718

    Article  Google Scholar 

  6. Bloom, B.H.: Space/time trade-offs in hash coding with allowable errors. Commun. ACM 13(7), 422–426 (1970). https://doi.org/10.1145/362686.362692, https://doi.acm.org/10.1145/362686.362692

    Article  Google Scholar 

  7. Bonakdarpour, B., Navabpour, S., Fischmeister, S.: Time-triggered runtime verification. Form. Methods Syst. Des. 43(1), 29–60 (2013). https://doi.org/10.1007/s10703-012-0182-0

    Article  Google Scholar 

  8. Butko, A., et al.: A trace-driven approach for fast and accurate simulation of manycore architectures. In: The 20th Asia and South Pacific Design Automation Conference, pp. 707–712 (Jan 2015). https://doi.org/10.1109/ASPDAC.2015.7059093

  9. Falk, H., et al.: TACLeBench: a benchmark collection to support worst-case execution time research. In: Schoeberl, M. (ed.) 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). OpenAccess Series in Informatics (OASIcs), vol. 55, pp. 2:1–2:10. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany (2016). https://doi.org/10.4230/OASIcs.WCET.2016.2, http://drops.dagstuhl.de/opus/volltexte/2016/6895

  10. Goldberg, A., Havelund, K.: Instrumentation of java bytecode for runtime analysis. Technical Reports from ETH Zurich 408, ETH Zurich, Zurich, Switzerland (2003)

    Google Scholar 

  11. IEEE: IEEE standard for standard systemc language reference manual. Std 1666–2011 (Revision of IEEE Std 1666–2005), pp. 1–638, January 2012. https://doi.org/10.1109/IEEESTD.2012.6134619

  12. Jagtap, R., Diestelhorst, S., Hansson, A., Jung, M., Wehn, N.: Exploring system performance using elastic traces: fast, accurate and portable. In: IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July 2016, Samos Island, Greece (2016)

    Google Scholar 

  13. Jahic, J., Kuhn, T., Jung, M., Wehn, N.: Supervised testing of concurrent software in embedded systems. In: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp. 233–238, July 2017. https://doi.org/10.1109/SAMOS.2017.8344633

  14. Ji, W., Liu, Y., Huo, Y., Wang, Y., Shi, F.: Extracting threaded traces in simulation environments. In: Hsu, C.-H., Li, X., Shi, X., Zheng, R. (eds.) NPC 2013. LNCS, vol. 8147, pp. 27–38. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-40820-5_3

    Chapter  Google Scholar 

  15. Kane, A., Chowdhury, O., Datta, A., Koopman, P.: A case study on runtime monitoring of an autonomous research vehicle (ARV) system. In: Bartocci, E., Majumdar, R. (eds.) RV 2015. LNCS, vol. 9333, pp. 102–117. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-23820-3_7

    Chapter  Google Scholar 

  16. Kuhn, T., Forster, T., Braun, T., Gotzhein, R.: Feral - framework for simulator coupling on requirements and architecture level. In: 2013 Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2013), pp. 11–22, October 2013

    Google Scholar 

  17. Lamport, L.: Time, clocks, and the ordering of events in a distributed system. Commun. ACM 21(7), 558–565 (1978)

    Article  Google Scholar 

  18. Lattner, C., Adve, V.: Llvm: a compilation framework for lifelong program analysis & transformation. In: International symposium on Code Generation and Optimization: Feedback-Directed and Runtime Optimization. CGO 2004, p. 75. IEEE, San Jose (2004)

    Google Scholar 

  19. Li, H., De Meulenaere, P., Hellinckx, P.: Powerwindow: a multi-component taclebench benchmark for timing analysis. Advances on P2P, Parallel, Grid, Cloud and Internet Computing. LNDECT, vol. 1, pp. 779–788. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-49109-7_75

    Chapter  Google Scholar 

  20. Luk, C.K., et al.: Pin: Building customized program analysis tools with dynamic instrumentation. SIGPLAN Not. 40(6), 190–200, June 2005. https://doi.org/10.1145/1064978.1065034, https://doi.acm.org/10.1145/1064978.1065034

    Article  Google Scholar 

  21. Moosbrugger, P., Rozier, K.Y., Schumann, J.: R2u2: monitoring and diagnosis of security threats for unmanned aerial systems. Formal Methods in System Design 51(1), 31–61 (2017). https://doi.org/10.1007/s10703-017-0275-x

    Article  Google Scholar 

  22. Navabpour, S., Bonakdarpour, B., Fischmeister, S.: Time-triggered runtime verification of component-based multi-core systems. In: Bartocci, E., Majumdar, R. (eds.) RV 2015. LNCS, vol. 9333, pp. 153–168. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-23820-3_10

    Chapter  MATH  Google Scholar 

  23. Necula, G.C., McPeak, S., Rahul, S.P., Weimer, W.: CIL: intermediate language and tools for analysis and transformation of C programs. In: Horspool, R.N. (ed.) CC 2002. LNCS, vol. 2304, pp. 213–228. Springer, Heidelberg (2002). https://doi.org/10.1007/3-540-45937-5_16

    Chapter  Google Scholar 

  24. Nethercote, N., Seward, J.: Valgrind: A framework for heavyweight dynamic binary instrumentation. SIGPLAN Not. 42(6), 89–100 (2007). https://doi.org/10.1145/1273442.1250746, https://doi.acm.org/10.1145/1273442.1250746

    Article  Google Scholar 

  25. Nocua, A., Bruguier, F., Sassatelli, G., Gamatie, A.: Elasticsimmate: a fast and accurate gem5 trace-driven simulator for multicore systems. In: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). pp. 1–8, July 2017. https://doi.org/10.1109/ReCoSoC.2017.8016146

  26. Potter, B.: Supporting native pthreads in syscall emulation mode, June 2015. http://gem5.org/wiki/images/8/80/2015_ws_07_pthread.pdf

  27. Savage, S., Burrows, M., Nelson, G., Sobalvarro, P., Anderson, T.: Eraser: a dynamic data race detector for multithreaded programs. ACM Trans. Comput. Syst. 15(4), 391–411 (1997). https://doi.org/10.1145/265924.265927, https://doi.acm.org/10.1145/265924.265927

    Article  Google Scholar 

  28. Sheng, T., Vachharajani, N., Eranian, S., Hundt, R., Chen, W., Zheng, W.: Racez: a lightweight and non-invasive race detection tool for production applications. In: 2011 33rd International Conference on Software Engineering (ICSE), pp. 401–410, May 2011. https://doi.org/10.1145/1985793.1985848

  29. Song, Y.W., Lee, Y.H.: On the existence of probe effect in multi-threaded embedded programs. In: International Conference on Embedded Software. EMSOFT. IEEE, Jaypee Greens, India (2014)

    Google Scholar 

  30. Vallée-Rai, R., Co, P., Gagnon, E., Hendren, L., Lam, P., Sundaresan, V.: Soot - a java bytecode optimization framework. In: Proceedings of the 1999 Conference of the Centre for Advanced Studies on Collaborative Research. pp. 13-. CASCON 1999. IBM Press (1999). http://dl.acm.org/citation.cfm?id=781995.782008

  31. Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The splash-2 programs: characterization and methodological considerations. In: Proceedings 22nd Annual International Symposium on Computer Architecture. pp. 24–36, June 1995. https://doi.org/10.1109/ISCA.1995.524546

  32. Zhou, P., Teodorescu, R., Zhou, Y.: Hard: Hardware-assisted lockset-based race detection. In: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture. pp. 121–132. HPCA ’07, IEEE Computer Society, Washington, DC, USA (2007). https://doi.org/10.1109/HPCA.2007.346191, https://doi.org/10.1109/HPCA.2007.346191

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Acknowledgments

This work was funded by the German Federal Ministry of Education and Research (BMBF) under grant no. 01IS16025 (ARAMiS II) and supported by the the Fraunhofer High Performance Center for Simulation- and Software-based Innovation. We thank Sonnhild Namingha from Fraunhofer IESE for reviewing this article.

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Authors and Affiliations

  1. Fraunhofer IESE, Fraunhofer-Platz 1, Kaiserslautern, Germany

    Jasmin Jahic, Matthias Jung & Thomas Kuhn

  2. Microelectronic Systems Design Research Group, University of Kaiserslautern, Erwin-Schroedinger-Strasse 1, Kaiserslautern, Germany

    Claus Kestel & Norbert Wehn

Authors
  1. Jasmin Jahic
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  2. Matthias Jung
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  3. Thomas Kuhn
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  4. Claus Kestel
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  5. Norbert Wehn
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Correspondence to Jasmin Jahic .

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Editors and Affiliations

  1. University of Malta, Msida, Malta

    Christian Colombo

  2. University of Lübeck, Lübeck, Germany

    Martin Leucker

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Jahic, J., Jung, M., Kuhn, T., Kestel, C., Wehn, N. (2018). A Framework for Non-intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration. In: Colombo, C., Leucker, M. (eds) Runtime Verification. RV 2018. Lecture Notes in Computer Science(), vol 11237. Springer, Cham. https://doi.org/10.1007/978-3-030-03769-7_28

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  • DOI: https://doi.org/10.1007/978-3-030-03769-7_28

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