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Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation

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Rough Sets (IJCRS 2019)

Part of the book series: Lecture Notes in Computer Science ((LNAI,volume 11499))

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Abstract

The rough sets theory developed by Prof. Z. Pawlak is one of the tools used in intelligent systems for data analysis and processing. In modern systems, the amount of the collected data is increasing quickly, so the computation speed becomes the critical factor. One of the solutions to this problem is data reduction. Removing the redundancy in the rough sets can be achieved with the reduct. Most of the algorithms of generating the reduct are only software implementations, therefore having many limitations coming from using the fixed word length, as well as consuming time for fetching and processing of the instruction and data. These limitations make the software-based implementations relatively slow. Unlike a software, the hardware systems can process the data faster than software. In this paper, the hardware implementation of the two-stage greedy algorithm to find the one reduct is presented. The first stage of the algorithm is calculating the core using the discernibility matrix, and the second is enriching the core with the attributes that are necessary to build the reduct. The presented algorithm was implemented in Field Programmable Gate Array (FPGA) as a digital device consisting of blocks that process the data in a single step. For the research purpose, the algorithm was also implemented in C language and run on a PC. The times of execution of the reduct calculation in hardware and software were considered. Obtained results show an increase in the speed of data processing.

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Acknowledgment

This work was supported by grant S/WI/1/2018 from Bialystok University of Technology and funded with resources for research by the Ministry of Science and Higher Education in Poland.

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Correspondence to Tomasz Grzes .

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Grzes, T., Kopczynski, M. (2019). Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation. In: Mihálydeák, T., et al. Rough Sets. IJCRS 2019. Lecture Notes in Computer Science(), vol 11499. Springer, Cham. https://doi.org/10.1007/978-3-030-22815-6_38

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  • DOI: https://doi.org/10.1007/978-3-030-22815-6_38

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