Abstract
This chapter introduces the reader to the SystemVerilog Assertions language and its role under SystemVerilog IEEE-1800 umbrella and the roadblocks to design verification productivity and solutions thereof and explains SVA evolution and sets the stage for the rest of the book.
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Mehta, A.B. (2020). Introduction. In: System Verilog Assertions and Functional Coverage. Springer, Cham. https://doi.org/10.1007/978-3-030-24737-9_1
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DOI: https://doi.org/10.1007/978-3-030-24737-9_1
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Publisher Name: Springer, Cham
Print ISBN: 978-3-030-24736-2
Online ISBN: 978-3-030-24737-9
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