Abstract
This work represents a high resolution and low jitter 5-bit Flash Time to Digital converter (TDC) which concurrently achieves low power and improved periodic jitter. To minimize quantization error τQ and attain high resolution, equally spaced flash TDC is calibrated with least mean square algorithm (LMS). The adaptive filtration minimizes the error which minimizes the delay variation among the delay cells of flash TDC. Further slow and accurate 5 bit SAR TDC is used to calibrate the proposed TDC. The implementation of TDC is done in 0.18um digital CMOS logic technology. The results show the resolution of measurement is 6 ps. The dynamic power consumption is 1.98 mW at 25 °C temperature and 1.8 V core voltage.
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The SMDP-C2SD provides a financial aid for execution of project. The project is being acknowledged gratefully.
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Sahani, J.K., Singh, A., Agarwal, A. (2020). A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems. In: Bi, Y., Bhatia, R., Kapoor, S. (eds) Intelligent Systems and Applications. IntelliSys 2019. Advances in Intelligent Systems and Computing, vol 1037. Springer, Cham. https://doi.org/10.1007/978-3-030-29516-5_20
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DOI: https://doi.org/10.1007/978-3-030-29516-5_20
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