Abstract
In the last few years, data rate requirement in on-board data handling for space missions has continuously grown, due to the presence of high resolution instruments. This lead the European Space Agency to start working on a new communication standard named SpaceFibre. It is able to fulfil a data rate of 6.25 Gbit/s per communication lane (up to 16 communication lanes). This work proposes the design of a SpaceFibre interface Application Specific Integrated Circuit. The block diagram of the system is presented, together with results in terms of area occupation and power consumption (excluding serialiser-deserialiser circuitry) after the synthesis on a 65 nm CMOS technology.
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Acknowledgements
IngeniArs SpaceFibre technologies have been developed in the framework of the project SIMPLE (Spacefibre IMPLementation design & test Equipment). This project has received funding from the European Unions Horizon 2020 research and innovation programme under Grant Agreement No. 757038.
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Nannipieri, P., Dinelli, G., Dello Sterpaio, L., Marino, A., Fanucci, L. (2020). Design of a SpaceFibre High-Speed Satellite Interface ASIC. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2019. Lecture Notes in Electrical Engineering, vol 627. Springer, Cham. https://doi.org/10.1007/978-3-030-37277-4_56
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DOI: https://doi.org/10.1007/978-3-030-37277-4_56
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