Abstract
Approximate logic synthesis is emerging as a promising avenue towards the development of efficient and high performance digital designs. Indeed, effective methodologies for the inexact simplification of arithmetic circuits have been introduced in recent years. Nonetheless, strategies enabling the integration of multiple approximate components to realise complex approximate hardware modules, able to maximise gains while controlling ensuing Quality-of-Service degradations, are still in their infancy. Against this backdrop, we herein describe a methodology to automatically distribute the error leeway assigned to a hardware design among its constituent operators. Our strategy is able to identify high-quality trade-offs among resource requirements, performance and exactness in digital implementations, across applications belonging to different domains, and without restrictions on the type and bit-width of their approximable arithmetic components.
This work has been partially supported ML-edge (grant no. 200020_182009 - 156397) project funded by the Swiss NSF and the MyPreHealth (grant no. 16073) project funded by Hasler Stiftung.
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Notes
- 1.
For simplicity, we focus on single-output DFGs. Multiple-outputs cases can nonetheless be addressed by considering each output in isolation, and then selecting the most stringent approximation constraint for each operation.
- 2.
The authors of [8] aim to bind approximable operations (with known approximability) to inexact functional units.
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Ansaloni, G., Scarabottolo, I., Pozzi, L. (2020). Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. In: Rincón, F., Barba, J., So, H., Diniz, P., Caba, J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science(), vol 12083. Springer, Cham. https://doi.org/10.1007/978-3-030-44534-8_2
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