Abstract
RRAM has emerged as a non-volatile and denser alternative to SRAM memory. Various RRAMs show a range of write energies related to write currents. The write current magnitude is proportional to the read current magnitude, which is inversely related to the read latency. Hence, lower write energy leads to higher read latency - producing a fundamental trade-off. This trade-off leads to a fast-read vs. low write power dilemma, hindering the application of RRAM to lower level cache. In this work, we propose a modified bitcell design to overcome this and analyze its impact on L1 instruction cache replacement. We propose a modification in conventional one selection transistor (1T) and RRAM (1R) based 1T1R cell by adding another transistor (i.e. 2T1R cell) to drive high current for fast read irrespective of the RRAM current magnitude. We demonstrate that the read latency vs. write energy trade-off is mitigated using circuit simulations. The impact of the 2T1R bit cell for a fast read and slow write is compared with SRAM and 1T1R scheme for L1 cache replacement. We report an energy-delay product (EDP) reduction of 82% for high performance and 53% for embedded architecture with SRAM comparable throughput. Thus, the fast read capability establishes the potential of RRAM as a lower-level cache substitute for both high performance and embedded applications.
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Lele, A., Jandhyala, S., Gangurde, S., Singh, V., Subramoney, S., Ganguly, U. (2022). Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_41
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