Abstract
The paper presents a new approach to functional, bit-level verification of arithmetic circuits. The circuit is modeled as a network of adders and basic Boolean gates, and the computation performed by the circuit is viewed as a flow of binary data through such a network. The verification problem is cast as a Network Flow problem and solved using symbolic term rewriting and simple algebraic techniques. Functional correctness is proved by showing that the symbolic flow computed at the primary inputs is equal to the flow computed at the primary outputs. Experimental results show a potential application of the method to certain classes of arithmetic circuits.
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Ciesielski, M., Brown, W., Rossi, A. (2013). Arithmetic Bit-Level Verification Using Network Flow Model. In: Bertacco, V., Legay, A. (eds) Hardware and Software: Verification and Testing. HVC 2013. Lecture Notes in Computer Science, vol 8244. Springer, Cham. https://doi.org/10.1007/978-3-319-03077-7_22
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DOI: https://doi.org/10.1007/978-3-319-03077-7_22
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-03076-0
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