Abstract
Modern automatic analytical methods for studying range and accuracy in fixed-point systems are gradually replacing the traditional bit-true fixed-point simulations used in Word-Length Optimization (WLO) problems. But these models have several limitations that must be overcome if they are going to be used in real world applications. When targeting large systems, the mathematical expressions quickly become too large to be handled in reasonable times by numerical engines. This paper proposes adapting the classical Fiduccia-Mattheyses partitioning algorithm to the WLO domain to automatically generate hierarchical partitions of the systems to quantize. This is the first time this type of algorithms are used for this purpose. The algorithm has been successfully applied to large problems that could not be addressed before. It generates, in the order of minutes, maneuverable sub-problems where state-of-the-art models can be applied. Thus, scalability is achieved and the impact of the problem size as a constraint is minimized.
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Shi, C., Brodersen, R.W.: A perturbation theory on statistical quantization effects in fixed-point DSP with non-stationary inputs. In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, vol. 3, p. III–373. IEEE (2004)
López, J.A., Caffarena, G., Carreras, C., Nieto-Taladriz, O.: Fast and accurate computation of the round-off noise of linear time-invariant systems. IET Circuits, Devices & Systems 2(4), 393 (2008)
Shou, H., Lin, H., Martin, R.R., Wang, G.: Modified affine arithmetic in tensor form for trivariate polynomial evaluation and algebraic surface plotting. Journal of Computational and Applied Mathematics 195(1-2), 155–171 (2006)
Parashar, K., Rocher, R., Menard, D., Sentieys, O.: A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. In: 23rd International Conference on VLSI Design, pp. 318–323. IEEE (2010)
Esteban, L., López, J., Sedano, E., Hernandez-Montero, S., Sanchez, M.: Quantization analysis of the infrared interferometer of the tj-ii stellarator for its optimized fpga-based implementation. IEEE Transactions on Nuclear Science 60, 3592–3596 (2013)
Fiduccia, C., Mattheyses, R.: A linear-time heuristic for improving network partitions. In: 19th Conference on Design Automation, pp. 241–247 (1982)
López, J.A., Sedano, E., Esteban, L., Caffarena, G., Fernández-Herrero, A., Carreras, C.: Applications of Interval-Based Simulations to the Analysis and Design of Digital LTI Systems. In: Cuadrado-Laborde, C. (ed.) Applications of Digital Signal Processing. Number i, 1st edn., pp. 279–296. InTech (2011)
Sarbishei, O., Radecka, K., Zilic, Z.: Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(3), 343–355 (2012)
Esteban, L., López, J.A., Sedano, E., Sánchez, M.: Quantization Analysis of the Infrared Interferometer of the TJ-II for its Optimized FPGA-based Implementation. In: IEEE 18th Real Time Conference, RTC 2012, Berkeley, California, USA (2012)
Kernighan, B., Lin, S.: An Efficient Heuristic Procedure for Partitioning Graphs. The Bell System Technical Journal 49(1), 291–307 (1970)
Hall, K.M.: An r-Dimensional Quadratic Placement Algorithm. Management Science 17(3), 219–229 (1970)
Tsay, R.S., Kuh, E.: A unified approach to partitioning and placement (VLSI layout). IEEE Transactions on Circuits and Systems 38(5), 521–533 (1991)
Bui, T.N., Moon, B.R.: Genetic algorithm and graph partitioning. IEEE Transactions on Computers 45(7), 841–855 (1996)
Johnson, E.L., Mehrotra, A., Nemhauser, G.L.: Min-cut clustering. Mathematical Programming 62, 133–151 (1993)
Alpert, C.J., Kahng, A.B.: Recent directions in netlist partitioning: a survey. The VLSI Journal on Integration 19(1-2), 1–81 (1995)
Kim, J., Hwang, I., Kim, Y.H., Moon, B.R.: Genetic approaches for graph partitioning: a survey. In: Proceedings of the 13th Annual Conference on Genetic and Evolutionary Computation, pp. 473–480. ACM (2011)
Krishnamurthy, B.: An Improved Min-Cut Algonthm for Partitioning VLSI Networks. IEEE Transactions on Computers C-33(5), 438–446 (1984)
Sanchis, L.: Multiple-way network partitioning with different cost functions. IEEE Transactions on Computers 42(12), 1500–1504 (1993)
Johnson, D.S., Aragon, C.R., McGeoch, L.A., Schevon, C.: Optimization by Simulated Annealing: An Experimental Evaluation; Part I, Graph Partitioning. Operations Research 37(6), 865–892 (1989)
Berge, C.: Graphs and Hypergraphs. Elsevier (1976)
Mathews, V.J., Sicuranza, G.L.: Polynomial Signal Processing. Wiley (2000)
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Sedano, E., Menard, D., López, J.A. (2014). Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds) Reconfigurable Computing: Architectures, Tools, and Applications. ARC 2014. Lecture Notes in Computer Science, vol 8405. Springer, Cham. https://doi.org/10.1007/978-3-319-05960-0_12
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DOI: https://doi.org/10.1007/978-3-319-05960-0_12
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