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Memories for NTC

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Near Threshold Computing

Abstract

This chapter focuses on a review of state-ofthe- art memory designs and new design methods for near-threshold computing (NTC). In particular, it provides a survey of existing low voltage memory techniques and their pros and cons. It also presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is validated by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-Vt voltage level as the digital logic. Reliability degradation is thus Overcome, which opens the path to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to a view of the future evolution towards 14, 10 and 7 nm technology nodes.

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Acknowledgments

This work was partially supported by the EU FP7 Project Phidias (GA n. 318013) and IMEC’s IIAP program.

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Correspondence to Tobias Gemmeke .

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Gemmeke, T., Sabry, M.M., Stuijt, J., Schuddinck, P., Raghavan, P., Catthoor, F. (2016). Memories for NTC. In: Hübner, M., Silvano, C. (eds) Near Threshold Computing. Springer, Cham. https://doi.org/10.1007/978-3-319-23389-5_5

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  • DOI: https://doi.org/10.1007/978-3-319-23389-5_5

  • Publisher Name: Springer, Cham

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